ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 92

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9-34. TX Power Ramping Control for RF Front-Ends
9.8.5 RX Frame Time Stamping
9.8.6 Configurable Start-Of-Frame Delimiter (SFD)
9.8.7 Dynamic Frame Buffer Protection
92
TRX_STATE
SLPTR
PA buffer
PA
M odulation
DIG 3
DIG 4
ATmega128RFA1
PLL_O N
0
2
The start-up sequence of the individual building blocks of the internal transmitter is
shown in the previous figure. The transmission is actually initiated by writing ‘1’ to
SLPTR. The radio transceiver state changes from PLL_ON to BUSY_TX and the PLL
settles to the transmit frequency within 16 µs (parameter tTR23 at page 43). The
modulation starts 16
buffer and the internal PA are enabled during this time.
The control of an external PA is done via the differential pin pair DIG3 and DIG4.
DIG3 = H / DIG4 = L indicates that the transmission starts and can be used to enable
an external PA. The timing of pins DIG3/DIG4 can be adjusted relative to the start of the
frame and the activation of the internal PA buffer. This is controlled using the register
bits PA_BUF_LT and PA_LT. For details refer to
To determine the exact timing of an incoming frame e.g. for beaconing networks, the
Symbol Counter should be used. SFD Time Stamping is enabled by setting bit SCTSE
of the Symbol Counter Control Register SCCR0. The actual 32 Bit Symbol Counter
value is captured in the SFD Time Stamp register SCTSR at the time, the SFD has
been received. For details see section
page
The SFD is a field indicating the end of the SHR and the start of the packet data. The
length of the SFD is 1 octet (2 symbols). This octet is used for byte synchronization only
and is not included in the Frame Buffer.
The value of the SFD could be changed if it is needed to operate non IEEE 802.15.4
compliant networks. An IEEE 802.15.4 compliant network node does not synchronize to
frames with a different SFD value.
The register SFD_VALUE contains the one octet start-of-frame delimiter (SFD) to
synchronize to a received frame. It is not recommended to set the low-order 4 bits to 0
due to the way the SHR is formed.
The ATmega128RFA1 continues the reception of incoming frames as long as it is in
any receive state. When a frame was successfully received and stored into the Frame
Buffer, the following frame will overwrite the Frame Buffer content again. To relax the
timing requirements for a Frame Buffer read access the Dynamic Frame Buffer
136.
4
6
s (parameter tTR10 at page 43) after the SLPTR=1. The PA
8
BU SY_TX
10
PA_BUF_LT
"SFD and Beacon Timestamp Generation" on
12
Figure 9-22 on page
14
PA_LT
16
1
1
0
8266B-MCU Wireless-03/11
1
78.
18
1
0 0
Length [µs]
1
1