ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 253

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.6.2 Noise Canceller
18.6.3 Using the Input Capture Unit
18.7 Output Compare Units
8266B-MCU Wireless-03/11
clock cycles. Note that the input of the noise canceller and edge detector is always
enabled unless the Timer/Counter is set in a Waveform Generation mode that uses
ICRn to define TOP.
An input capture can be software-triggered by controlling the port of the ICPn pin.
The noise canceller improves noise immunity by using a simple digital filtering scheme.
The noise canceller input is monitored over four samples and all four must be equal for
changing the output that in turn is used by the edge detector.
The noise canceller is enabled by setting the Input Capture Noise Canceller (ICNCn) bit
in Timer/Counter Control Register B (TCCRnB). When enabled the noise canceller
introduces additional four system clock cycles of delay from a change applied to the
input to the update of the ICRn Register. The noise canceller uses the system clock and
is therefore not affected by the prescaler.
The main challenge when using the Input Capture unit is to assign enough processor
capacity for handling the incoming events. The time between two events is critical. The
ICRn will be overwritten with a new value if the processor has not read the captured
value in the ICRn Register before the next event occurs. In this case the result of the
capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in
the interrupt handler routine as possible. Even though the Input Capture interrupt has
relatively high priority, the maximum interrupt response time is dependent on the
maximum number of clock cycles it takes to handle any of the other interrupt requests.
It is not recommended to use the Input Capture unit in any mode of operation where the
TOP value (resolution) is actively changed while counting.
Measurement of the duty cycle of an external signal requires that the trigger edge is
changed after each capture. Changing the edge sensing must be done as early as
possible after the ICRn Register has been read. After a change of the edge, the Input
Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICFn Flag is not required (if
an interrupt handler is used).
The 16-bit comparator continuously compares TCNTn with the Output Compare
Register (OCRnx). If TCNTn equals OCRnx the comparator signals a match. A match
will set the Output Compare Flag (OCFnx) at the next clock cycle of the timer. If
enabled (OCIEnx = 1), the Output Compare Flag generates an Output Compare
interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed.
Alternatively the OCFnx Flag can be software-cleared by writing a logical one to its I/O
bit location. The Waveform Generator uses the match signal to generate an output
according to the Waveform Generation mode bits (WGMn3:0) and Compare Output
mode bits (COMnx1:0). The TOP and BOTTOM signals are used by the Waveform
Generator for handling the special cases of the extreme values in some modes of
operation (see
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP
value i.e., the counter resolution. In addition to the counter resolution, the TOP value
defines the period time for waveforms generated by the Waveform Generator.
"Modes of Operation" on
page 257).
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