ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 60

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9-13. Example Timing of a TX_ARET Transaction
9.4.2.6 Interrupt Handling
60
FrameType
TRX_STATE
RX/TX
SLPTR
IRQ
Typ. Processing Delay
ATmega128RFA1
TX_ARET_ON
0
CSMA-CA
t
CSM A-CA
Note that if no ACK is expected (according to the content of the received frame in the
Frame Buffer), the radio transceiver issues a TRX24_TX_END interrupt directly after
the frame transmission has been completed. The value of the bits TRAC_STATUS of
register TRX_STATE is set to SUCCESS.
A value of MAX_CSMA_RETRIES = 7 initiates an immediate TX_ARET transaction
without performing CSMA-CA. This is required to support slotted acknowledgement
operation. Further the value MAX_FRAME_RETRIES is ignored and the TX_ARET
transaction is performed only once.
A timing example of a TX_ARET transaction is shown in
Here an example data frame of length 10 with an ACK request is transmitted, see
9-13 on
and expects an acknowledgement response. During the whole transaction including
frame transmit, wait for ACK and ACK receive the radio transceiver status register
TRX_STATUS signals BUSY_TX_ARET.
A successful reception of the acknowledgment frame is indicated by the
TRX24_TX_END interrupt. The status register TRX_STATUS changes back to
TX_ARET_ON. The TX_ARET status register TRAC_STATUS changes as well to
TRAC_STATUS = SUCCESS or TRAC_STATUS = SUCCESS_DATA_PENDING if the
frame pending subfield of the received ACK frame was set to 1.
The interrupt handling in the Extended Operating Mode is similar to the Basic Operating
Mode (see section
interrupts by setting the appropriate bit in register IRQ_MASK.
For RX_AACK and TX_ARET the following interrupts
about the status of a frame reception and transmission:
128
Note:
Value
16 µs
5
7
Data Frame (Length = 10, ACK=1)
page 61. After the transmission the radio transceiver switches to receive mode
1. t
CSMA-CA
Name
NO_ACK
INVALID
TX
TX
defines the random CSMA-CA processing time.
"Interrupt Handling" on
BUSY_TX_ARET
672
32 µs
x
Description
No acknowledgement frames were received
during all retry attempts
Entering TX_ARET mode sets
TRAC_STATUS = 7
page 39). The microcontroller enables
RX
RX
ACK Frame
(Table 9-13 on
Figure 9-13 below
x+352
8266B-MCU Wireless-03/11
TX_ARET_ON
RX_END
t
IRQ
page 61) inform
time [µs]
.
Table