ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 439

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.5 Using the Boundary-scan Chain
28.6 Using the On-chip Debug System
8266B-MCU Wireless-03/11
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected
As shown in the state diagram, the Run-Test/Idle state need not be entered between
selecting JTAG instruction and using Data Registers, and some JTAG instructions may
select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an
Idle state.
Note that independent of the initial state of the TAP Controller, the Test-Logic-Reset
state can always be entered by holding TMS high for five TCK clock periods. For
detailed information on the JTAG specification, refer to the literature listed in
"Bibliography" on
A complete description of the Boundary-scan capabilities are given in the section
1149.1 (JTAG) Boundary-scan" on page
The on-chip debug system must be disabled for the best RF performance of the radio
transceiver. As shown in Figure 28-1, the hardware support for on-chip debugging
consists mainly of
• A scan chain on the interface between the internal AVR CPU and the internal
• Breakpoint unit.
• Communication interface between the CPU and JTAG system.
All read or modify/write operations needed for implementing the debugger are done by
applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the
result to an I/O memory mapped location which is part of the communication interface
between the CPU and the JTAG system.
The Breakpoint Unit implements Break on Change of Program Flow, Single Step Break,
two program memory breakpoints and two combined breakpoints. Together, the four
breakpoints can be configured as either:
• 4 single program memory breakpoints;
• 3 single program memory breakpoint + 1 single data memory breakpoint;
• 2 single program memory breakpoints + 2 single data memory breakpoints;
selects a particular Data Register as path between TDI and TDO and controls the
circuitry surrounding the selected Data Register.
is latched onto the parallel output from the Shift Register path in the Update-IR state.
The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state
machine.
Shift Data Register – Shift-DR state. While in this state, upload the selected Data
Register (selected by the present JTAG instruction in the JTAG Instruction Register)
from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state,
the TMS input must be held low during input of all bits except the MSB. The MSB of
the data is shifted in when this state is left by setting TMS high. While the Data
Register is shifted in from the TDI pin, the parallel inputs to the Data Register
captured in the Capture-DR state is shifted out on the TDO pin.
Data Register has a latched parallel-output, the latching takes place in the Update-
DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating
the state machine.
peripheral units.
page 441.
442.
ATmega128RFA1
"IEEE
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