ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 85

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.7.1 Frame Receive Procedure
9.7.2 Frame Transmit Procedure
8266B-MCU Wireless-03/11
A frame reception comprises of two actions: The PHY listens for a frame, receives and
demodulates the frame to the Frame Buffer and signalizes its reception to the
application software. The application software reads the available frame data from the
Frame Buffer after or during the progress of the frame reception.
While in state RX_ON or RX_AACK_ON the radio transceiver searches for incoming
frames on the selected channel. First a TRX24_RX_START interrupt indicates the
detection of an IEEE 802.15.4 compliant frame assuming the appropriate interrupts are
enabled. The frame reception is completed when issuing the TRX24_RX_END
interrupt.
Different Frame Buffer read access scenarios are recommended for:
• Non-time critical applications: read access starts after the TRX24_RX_END interrupt;
• Time-critical applications: read access starts after the TRX24_RX_START interrupt;
The controller must ensure to read valid Frame Buffer contents. Reading frame data
before frame reception is finished can lead to invalid data, if buffer regions are
accessed which are not yet updated with the new frame.
While receiving a frame the data needs to be primarily stored in the Frame Buffer
before reading it. This is ensured by accessing the first Frame Buffer byte at least 32 µs
after the TRX24_RX_START interrupt.
It is recommended for operations considered to be not time-critical to wait for the
TRX24_RX_END interrupt before starting a Frame Buffer read access. The following
figure illustrates the frame receive procedure using the TRX24_RX_END interrupt.
Figure 9-27. Transactions between radio transceiver and microcontroller during receive
Critical protocol timing could require starting the Frame Buffer read access after the
TRX24_RX_START interrupt. The first byte of the frame data can be read 32 µs after
the TRX24_RX_START interrupt. The application software must ensure to read slower
than the frame is received. Otherwise a Frame Buffer under-run occurs and the frame
data may be not valid.
A frame transmission comprises of the two actions Frame Buffer write access and
transmission of the Frame Buffer content. Both actions can be run in parallel if required
by critical protocol timing.
Figure 9-28 on
and transmitting the frame. The frame transmission is initiated writing SLPTR or writing
page 86 illustrates the frame transmit procedure by consecutively writing
Read frame data (Frame Buffer access)
Read TST_FRAME_LENGTH register
IRQ issued (RX_START)
IRQ issued (RX_END)
(Register access)
ATmega128RFA1
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