ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 440

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.7 On-chip Debug Specific JTAG Instructions
28.7.1 PRIVATE0; 0x8
28.7.2 PRIVATE1; 0x9
28.7.3 PRIVATE2; 0xA
28.7.4 PRIVATE3; 0xB
28.8 Using the JTAG Programming Capabilities
440
ATmega128RFA1
• 2 single program memory breakpoints + 1 program memory breakpoint with mask
• 2 single program memory breakpoints + 1 data memory breakpoint with mask
A debugger, like the AVR Studio, may however use one or more of these resources for
its internal purpose, leaving less flexibility to the end-user.
A list of the on-chip debug specific JTAG instructions is given in
Specific JTAG Instructions"
The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In
addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the
on-chip debug system to work. As a security feature, the on-chip debug system is
disabled when either of the LB1 or LB2 Lock-bits are set. Otherwise, the on-chip debug
system would have provided a back-door into a secured device.
The AVR Studio enables the user to fully control execution of programs on an AVR
device with on-chip debug capability, AVR In-Circuit Emulator, or the built-in AVR
Instruction Set Simulator. AVR Studio supports source level execution of Assembly
programs assembled with Atmel Corporation’s AVR Assembler and C programs
compiled with third party vendors’ compilers. For a full description of the AVR Studio,
please refer to the AVR Studio User Guide. Only highlights are presented in this
document.
All necessary execution commands are available in AVR Studio, both on source level
and on disassembly level. The user can execute the program, single step through the
code either by tracing into or stepping over functions, step out of functions, place the
cursor on a statement and execute until the statement is reached, stop the execution,
and reset the execution target. In addition, the user can have an unlimited number of
code breakpoints (using the BREAK instruction) and up to two data memory
Breakpoints, alternatively combined as a mask (range) breakpoint.
The on-chip debug support is considered being private JTAG instructions, and
distributed within ATMEL and to selected third party vendors only. Instruction operation
codes are listed for reference.
Private JTAG instruction for accessing on-chip debug system;
Private JTAG instruction for accessing on-chip debug system;
Private JTAG instruction for accessing on-chip debug system;
Private JTAG instruction for accessing on-chip debug system;
Programming of the ATmega128RFA1 via JTAG is performed via the 4-pin JTAG port,
TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled and
observed to perform JTAG programming (in addition to power pins). The JTAGEN Fuse
must be programmed and the JTD bit in the MCUCR Register must be cleared to
enable the JTAG Test Access Port.
(“range breakpoint”).
(“range breakpoint”).
below.
8266B-MCU Wireless-03/11
"On-chip Debug