ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 223

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.2.3 EIMSK – External Interrupt Mask Register
16.2.4 EIFR – External Interrupt Flag Register
8266B-MCU Wireless-03/11
When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control
bits in the External Interrupt Control Registers EICRA and EICRB define whether the
External Interrupt is activated on rising or falling edge or level sensed. Activity on any of
these pins will trigger an interrupt request even if the pin is enabled as an output. This
provides a way of generating a software interrupt.
• Bit 7:0 – INT7:0 - External Interrupt Request Enable
Table 16-135 INT Register Bits
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit
INT7:0 in EIMSK are set (one), the MCU will jump to the interrupt vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical one to it. These flags are always cleared when INT7:0 are configured
as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts
disabled, the input buffers on these pins will be disabled. This may cause a logic
change in internal signals which will set the INTF3:0 flags. See "Digital Input Enable
and Sleep Modes" for more information.
• Bit 7:0 – INTF7:0 - External Interrupt Flag
Table 16-136 INTF Register Bits
Bit
$1D ($3D)
Read/Write
Initial Value
Bit
$1C ($3C)
Read/Write
Initial Value
Register Bits
INT7:0
Register Bits
INTF7:0
INTF7
INT7
RW
RW
7
0
7
0
INTF6
INT6
RW
RW
6
0
6
0
INTF5
INT5
RW
RW
5
0
5
0
Value
Value
0x00
0x00
0x01
0x02
0x80
0xff
INTF4
INT4
RW
RW
4
0
4
0
Description
All external pin interrupts are disabled.
All external pin interrupts are enabled.
Description
No edge or logic change on INT7:0
occurred.
A edge or logic change on INT0 occurred
and triggered an interrupt request.
...
A edge or logic change on INT7 occurred
and triggered an interrupt request.
INTF3
INT3
RW
RW
3
0
3
0
ATmega128RFA1
INTF2
INT2
RW
RW
2
0
2
0
INTF1
INT1
RW
RW
1
0
1
0
INTF0
INT0
RW
RW
0
0
0
0
EIMSK
EIFR
223