ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 201

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8266B-MCU Wireless-03/11
Table 14-12. Port F Pins Alternate Functions
Port Pin
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7.
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or
Data Register (scan chains). When the JTAG interface is enabled, this pin can not be
used as an I/O pin.
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data
Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5.
TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-
controller state machine. When the JTAG interface is enabled, this pin can not be used
as an I/O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG
interface is enabled, this pin can not be used as an I/O pin.
• DIG4, ADC3 – Port F, Bit 3
ADC3, Analog to Digital Converter, Channel 3.
DIG4, Radio Transceiver RX/TX Indicator Output: If the bit PA_EXT_EN in
TRX_CTRL_1 is set to one then the PF3 pin serves as the Radio Transceiver
receive/transmit indicator output to control an external RF front-end.
• DIG2, ADC2 – Port F, Bit 2
ADC2, Analog to Digital Converter, Channel 2.
DIG2,
ANT_EXT_SW_EN in ANT_DIV is set to one then the PF2 pin serves as a Radio
Transceiver output to control External Antenna Diversity.
• ADC1 – ADC0 – Port F, Bit 1:0
Analog to Digital Converter, Channel 1:0.
Radio
Alternate Function
ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)
ADC4/TCK (ADC input channel 4 or JTAG Test Clock)
ADC3/DIG4 (ADC input channel 3 or Radio Transceiver RX/TX Indicator
Output)
ADC2/DIG2 (ADC input channel 2 or Radio Transceiver Antenna Diversity
Control Output)
ADC1 (ADC input channel 1)
ADC0 (ADC input channel 0)
Transceiver
Antenna
Diversity
ATmega128RFA1
Control
Output:
If
the
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