ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 507

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

34.8 2-wire Serial Interface Characteristics
Table 34-8. 2-wire Serial Bus Requirements
8266B-MCU Wireless-03/11
Symbol
t
t
Symbol
V
V
V
V
t
t
t
I
C
f
Rp
t
t
t
t
t
t
t
DVREG
DVREG
r
of
SP
i
SCL
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
(1)
IL
IH
hys
OL
i
(1)
(1)
(1)
(1)
(1)
Parameter
Input Low-voltage
Input High-voltage
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
Rise Time for both SDA and SCL
Output Fall Time from V
Spikes suppressed by the input filter
Input current each I/O Pin
Capacitance for each I/O Pin
SCL Clock frequency
Value of Pull-up resistor
Hold time (repeated) START condition
Low period of the SCL clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Date setup time
Setup time for STOP condition
Parameter
Power up time DVREG
Power up time DVREG
IHmin
Table 34-8 below
Bus. The ATmega128RFA1 2-wire Serial Interface meets or exceeds these
requirements under the noted conditions.
Timing symbols refer to
to V
ILmax
Condition
Startup after Power-On
C
C
Startup after DEEP_SLEEP
C
DVDD
DVDD
DVDD
= 100 nF
= 1 µF
= 100 nF… 1 µF
describes the requirements for devices connected to the 2-wire Serial
Condition
3 mA sink current
10 pF < C
0.1V
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
CK
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
(4)
Figure 34-2 on
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
DD
>max(16f
< V
b
i
< 400 pF
< 0.9V
SCL
(6)
(7)
,250 kHz)
DD
(3)
page 508.
(5)
20+0.1C
20+0.1C
0.05V
V
V
0.7V
DD
DD
ATmega128RFA1
3mA
3mA
Min
-0.5
250
100
-10
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
4.0
0.6
0
0
0
0
0
-0.4V
-0.4V
DD
DD
Min.
b
b
(2)
(2,3)
(2,3)
V
Typ.
1000 ns
0.3V
300 ns
40
60
10
DD
Max
50
300
250
400
0.4
10
10
C
C
+0.5
(2)
b
b
DD
Max.
Units
kHz
µA
Units
pF
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
V
V
V
V
µs
µs
µs
507