ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 218

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is
programmed. If this bit is one, the JTAG interface is disabled. In order to avoid
unintentional disabling or enabling of the JTAG interface, a timed sequence must be
followed when changing this bit: The application software must write this bit to the
desired value twice within four cycles to change its value. Note that this bit must not be
altered when using the On-chip Debug system.
• Bit 6:5 – Res1:0 - Reserved
• Bit 4 – PUD - Pull-up Disable
When this bit is written to one, the I/O ports pull-up resistors are disabled even if the
DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn,
PORTxn} = 2'b01). See section "Ports as General Digital I/O" for more details about this
feature.
• Bit 3:2 – Res1:0 - Reserved
• Bit 1 – IVSEL - Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the
beginning of the Boot Loader section of the Flash. The actual address of the start of the
Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section "Memory
Programming" for details. To avoid unintentional changes of Interrupt Vector tables, a
special write procedure must be followed to change the IVSEL bit (see section "Moving
Interrupts Between Application and Boot Section" for details): 1. Write the Interrupt
Vector Change Enable (IVCE) bit to one; 2. Within four cycles, write the desired value
to IVSEL while writing a zero to IVCE. Interrupts will be automatically disabled while this
sequence is executed. Interrupts are disabled in the same cycle IVCE is set, and they
remain disabled until after the instruction following the write to IVSEL. If IVSEL is not
written, interrupts remain disabled for four cycles. The I-bit in the Status Register is
unaffected by the automatic disabling. Note that if Interrupt Vectors are placed in the
Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled
while executing from the Application section. If Interrupt Vectors are placed in the
Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section.
• Bit 0 – IVCE - Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is
cleared by hardware four cycles after it is written or when IVSEL is written. Setting the
IVCE bit will disable interrupts as explained in the IVSEL description.
ATmega128RFA1
218
8266B-MCU Wireless-03/11