ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 395

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 25-5. Status Codes for Slave Receiver Mode
8266B-MCU Wireless-03/11
0x60
0x68
0x70
Status Code
Prescaler
Bits are 0
(TWSR)
Serial Bus and 2-wire
Own SLA+W has been
received; ACK has been
returned
Arbitration lost in
SLA+R/W as Master;
own SLA+W has been
received; ACK has been
returned
General call address has
been received; ACK has
been returned
Status of the 2-wire
Serial Interface
Hardware
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the TWI will respond to the general call
address (0x00), otherwise it will ignore the general call address.
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one
to enable the acknowledgement of the device’s own slave address or the general call
address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its
own slave address (or the general call address if enabled) followed by the data direction
bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode
is entered. After its own slave address and the write bit have been received, the TWINT
Flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each
status code is detailed in
entered if arbitration is lost while the TWI is in the Master mode (see states 0x68 and
0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”)
to SDA after the next received data byte. This can be used to indicate that the Slave is
not able to receive any more bytes. While TWEA is zero, the TWI does not
acknowledge its own slave address. However, the 2-wire Serial Bus is still monitored
and address recognition may resume at any time by setting TWEA. This implies that the
TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the
TWEA bit is set, the interface can still acknowledge its own slave address or the
general call address by using the 2-wire Serial Bus clock as a clock source. The part
will then wake up from sleep and the TWI will hold the SCL clock low during the wake
up and until the TWINT Flag is cleared (by writing it to one). Further data reception will
be carried out as normal, with the AVR clocks running as normal. Observe that if the
AVR is set up with a long start-up time, the SCL line may be held low for a long time,
blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last
byte present on the bus when waking up from these Sleep modes.
TWCR
Value
To/from TWDR
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
TWINT
0
Application Software Response
TWEA
1
STA
Table 25-5
X
X
X
X
X
X
TWSTA
STO
0
0
0
0
0
0
0
To TWCR
below. The Slave Receiver mode may also be
TWINT
TWSTO
1
1
1
1
1
1
0
TWEA
TWWC
0
1
0
1
0
1
ATmega128RFA1
0
Next Action Taken by TWI
Hardware
Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
TWEN
1
–
0
TWIE
X
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