ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 375
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 375 of 555
- Download datasheet (6Mb)
24.6.4 UCSR0B – USART0 MSPIM Control and Status Register B
24.6.5 UCSR0C – USART0 MSPIM Control and Status Register C
8266B-MCU Wireless-03/11
• Bit 5 – UDRE0 - USART Data Register Empty
The UDRE0 Flag indicates if the transmit buffer (UDR0) is ready to receive new data. If
UDRE0 is one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag
can generate a Data Register Empty interrupt (see description of the UDRIE0 bit).
UDRE0 is set after a reset to indicate that the Transmitter is ready.
• Bit 7 – RXCIE0 - RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC0 Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXC0 bit in UCSR0A is set.
• Bit 6 – TXCIE0 - TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC0 Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXC0 bit in UCSR0A is set.
• Bit 5 – UDRIE0 - USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Empty
interrupt will be generated only if the UDRIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE0 bit in UCSR0A is set.
• Bit 4 – RXEN0 - Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will
override normal port operation for the RxD0 pin when enabled. Disabling the Receiver
will flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting
RXEN0=1 and TXEN0=0) has no meaning since it is the transmitter that controls the
transfer clock and since only master mode is supported.
• Bit 3 – TXEN0 - Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override
normal port operation for the TxD0 pin when enabled. The disabling of the Transmitter
(writing TXEN0 to zero) will not become effective until ongoing and pending
transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will no
longer override the TxD0 port.
• Bit 2 – UDORD0 - Data Order
Bit
NA ($C1)
Read/Write
Initial Value
Bit
NA ($C2)
Read/Write
Initial Value
RXCIE0
RW
7
0
7
TXCIE0
RW
6
6
0
UDRIE0
RW
5
5
1
RXEN0
RW
4
4
0
TXEN0
RW
3
3
0
ATmega128RFA1
UDORD0 UCPHA0 UCPOL0
RW
2
1
2
RW
1
1
1
RW
0
0
0
UCSR0B
UCSR0C
375
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