ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 122

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.25 FTN_CTRL – Transceiver Filter Tuning Control Register
9.12.26 PLL_CF – Transceiver Center Frequency Calibration Control Register
122
ATmega128RFA1
Table 9-62 AACK_ACK_TIME Register Bits
• Bit 1 – AACK_PROM_MODE - Enable Promiscuous Mode
This register bit enables the promiscuous mode within the RX_AACK mode; refer to
IEEE 802.15.4-2006 chapter 7.5.6.5. If this bit is set, every incoming frame with a valid
PHR finishes with a RX_END interrupt even if the third level filter rules do not match or
the FCS is not valid. The bit RX_CRC_VALID of register PHY_RSSI is set accordingly.
If this bit is set and a frame passes the third level filter rules, an acknowledgment frame
is generated and transmitted unless disabled by bit AACK_DIS_ACK of register
CSMA_SEED_1.
• Bit 0 – Res - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
This register controls the operation of the calibration loop of the filter tuning network.
• Bit 7 – FTN_START - Start Calibration Loop of Filter Tuning Network
FTN_START = 1 initiates the calibration of the filter tuning network. When the
calibration cycle has finished after at most 25 µs the register bit is automatically reset to
0.
• Bit 6:0 – Resx6:0 - Reserved
Bit
NA ($158)
Read/Write
Initial Value
Bit
NA ($158)
Read/Write
Initial Value
Bit
NA ($15A)
Read/Write
Initial Value
Bit
NA ($15A)
Read/Write
Initial Value
Register Bits
AACK_ACK_TIME
FTN_START
Resx3
RW
RW
7
0
3
1
PLL_CF_START
Resx5
RW
RW
7
0
5
0
Resx6
Resx2
RW
RW
6
1
2
0
Value
0
1
Resx5
Resx1
Description
12 symbols acknowledgment time
RW
RW
2 symbols acknowledgment time
5
0
1
0
Resx6
Resx4
RW
RW
6
1
4
1
Resx4
Resx0
RW
RW
4
1
0
0
8266B-MCU Wireless-03/11
FTN_CTRL
FTN_CTRL
PLL_CF
PLL_CF