ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 224

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.2.5 PCICR – Pin Change Interrupt Control Register
16.2.6 PCIFR – Pin Change Interrupt Flag Register
224
ATmega128RFA1
• Bit 7:3 – Res4:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 2 – PCIE2 - Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is
executed from the PCI2 Interrupt Vector. PCINT23:16 pins are enabled individually by
the PCMSK2 Register. Note that the I/O ports corresponding to PCINT23:16 are not
implemented. Therefore PCIE2 has no function in this device.
• Bit 1 – PCIE1 - Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is
executed from the PCI1 Interrupt Vector. PCINT15:8 pins are enabled individually by
the PCMSK1 Register. Note that the I/O ports corresponding to PCINT15:9 are not
implemented.
• Bit 0 – PCIE0 - Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0
Register.
• Bit 7:3 – Res4:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 2 – PCIF2 - Pin Change Interrupt Flag 2
When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2
becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical
one to it. Note that the I/O ports corresponding to PCINT23:16 are not implemented.
Therefore PCIF2 has no function in this device.
Bit
NA ($68)
Read/Write
Initial Value
Bit
$1B ($3B)
Read/Write
Initial Value
Res4
Res4
R
R
7
0
7
0
Res3
Res3
R
R
6
0
6
0
Res2
Res2
R
R
5
0
5
0
Res1
Res1
R
R
4
0
4
0
Res0
Res0
R
R
3
0
3
0
PCIE2
PCIF2
RW
RW
2
0
2
0
PCIE1
PCIF1
RW
RW
1
0
1
0
8266B-MCU Wireless-03/11
PCIE0
PCIF0
RW
RW
0
0
0
0
PCICR
PCIFR