ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 359

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.10.4 UCSR0C – USART0 Control and Status Register C
8266B-MCU Wireless-03/11
Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Empty
interrupt will be generated only if the UDRIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE0 bit in UCSR0A is set.
• Bit 4 – RXEN0 - Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal
port operation for the RxD0 pin when enabled. Disabling the Receiver will flush the
receive buffer invalidating the FE0, DOR0 and UPE0 Flags.
• Bit 3 – TXEN0 - Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override
normal port operation for the TxD0 pin when enabled. The disabling of the Transmitter
(writing TXEN0 to zero) will not become effective until ongoing and pending
transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will no
longer override the TxD0 port.
• Bit 2 – UCSZ02 - Character Size
The UCSZ02 bits combined with the UCSZ01:0 bit in UCSR0C sets the number of data
bits (Character Size) in the frame that the Receiver and Transmitter use.
• Bit 1 – RXB80 - Receive Data Bit 8
RXB80 is the 9th data bit of the received character when operating with serial frames
with nine data bits. The bit must be read before reading the lower 8 bits from UDR0.
• Bit 0 – TXB80 - Transmit Data Bit 8
TXB80 is the 9th data bit in the character to be transmitted when operating with serial
frames with nine data bits. The bit must be written before writing the lower 8 bits to
UDR0.
• Bit 7:6 – UMSEL01:00 - USART Mode Select
These bits select the mode of operation of the USART0 as shown in the following table.
See section "USART in SPI Mode" for a full description of the Master SPI Mode
(MSPIM) operation.
Table 23-4 UMSEL0 Register Bits
• Bit 5:4 – UPM01:00 - Parity Mode
These bits enable and set type of parity generation and check. If enabled, the
Transmitter will automatically generate and send the parity of the transmitted data bits
within each frame. The Receiver will generate a parity value for the incoming data and
Bit
NA ($C2)
Read/Write
Initial Value
Register Bits
UMSEL01:00
UMSEL01 UMSEL00 UPM01
RW
7
0
RW
6
0
RW
5
0
Value
0x00
0x01
0x02
0x03
UPM00
RW
4
0
Description
Asynchronous USART
Synchronous USART
Reserved
Master SPI (MSPIM)
USBS0
RW
3
0
ATmega128RFA1
UCSZ01 UCSZ00 UCPOL0 UCSR0C
RW
2
0
RW
1
1
RW
0
0
359