ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 364

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.10.10 UCSR1C – USART1 Control and Status Register C
364
ATmega128RFA1
The UCSZ12 bits combined with the UCSZ11:0 bit in UCSR1C sets the number of data
bits (Character Size) in the frame that the Receiver and Transmitter use.
• Bit 1 – RXB81 - Receive Data Bit 8
RXB81 is the 9th data bit of the received character when operating with serial frames
with nine data bits. The bit must be read before reading the lower 8 bits from UDR1.
• Bit 0 – TXB81 - Transmit Data Bit 8
TXB81 is the 9th data bit in the character to be transmitted when operating with serial
frames with nine data bits. The bit must be written before writing the lower 8 bits to
UDR1.
• Bit 7:6 – UMSEL11:10 - USART Mode Select
These bits select the mode of operation of the USART1 as shown in the following table.
See section "USART in SPI Mode" for a full description of the Master SPI Mode
(MSPIM) operation.
Table 23-9 UMSEL1 Register Bits
• Bit 5:4 – UPM11:10 - Parity Mode
These bits enable and set type of parity generation and check. If enabled, the
Transmitter will automatically generate and send the parity of the transmitted data bits
within each frame. The Receiver will generate a parity value for the incoming data and
compare it to the UPM1 setting. If a mismatch is detected, the UPE1 Flag in UCSR1A
will be set.
Table 23-10 UPM1 Register Bits
• Bit 3 – USBS1 - Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
Bit
NA ($CA)
Read/Write
Initial Value
Register Bits
UMSEL11:10
Register Bits
UPM11:10
UMSEL11 UMSEL10 UPM11
RW
7
0
RW
6
0
RW
5
0
Value
Value
0x00
0x01
0x02
0x03
0x00
0x01
0x02
0x03
UPM10
RW
4
0
Description
Asynchronous USART
Synchronous USART
Reserved
Master SPI (MSPIM)
Description
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
USBS1
RW
3
0
UCSZ11 UCSZ10 UCPOL1 UCSR1C
RW
2
1
RW
1
1
8266B-MCU Wireless-03/11
RW
0
0