ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 246

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.2.1 Registers
246
ATmega128RFA1
Figure 18-1. 16-bit Timer/Counter Block Diagram
The Timer/Counter (TCNTn) Output Compare Registers (OCRnA/B/C) and Input
Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed
when accessing the 16-bit registers. These procedures are described in the section
"Accessing 16-bit Registers" on
(TCCRnA/B/C) are 8-bit registers and have no CPU access restrictions. Interrupt
requests (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register
(TIFRn). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSKn). TIFRn and TIMSKn are not shown in the figure since these registers are
shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler or by an external clock
source on the Tn pin. The Clock Select logic block controls which clock source and
which clock edge the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the clock
select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the
Notes:
1. Refer to
198
Timer/Counter
TCCRnA
for Timer/Counter1, 2 and 3 pin placements and description.
OCRnA
OCRnB
TCNTn
ICRn
=
=
Figure 1-1 on page
Direction
Count
Clear
Control Logic
page 247. The Timer/Counter Control Registers
TOP
2,
=
TCCRnB
Table 14-3 on page 194
Values
BOTTOM
Fixed
TOP
ICFn (Int.Req.)
Tn
clk
Detector
).
Edge
=
(1)
Tn
0
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
Generation
Generation
( From Prescaler )
Waveform
Waveform
Canceler
Detector
Noise
and
Edge
8266B-MCU Wireless-03/11
Table 14-9 on page
Comparator Ouput )
( From Analog
OCnA
OCnB
ICPn
Tn