ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 376

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.6.6 UCSR1A – USART1 MSPIM Control and Status Register A
24.6.7 UCSR1B – USART1 MSPIM Control and Status Register B
376
ATmega128RFA1
When set to one the LSB of the data word is transmitted first. When set to zero the
MSB of the data word is transmitted first. Refer to section "Frame Formats" for details.
• Bit 1 – UCPHA0 - Clock Phase
The UCPHA0 bit setting determines if data is sampled on the leading (first) or tailing
(last) edge of XCK0. Refer to the section "SPI Data Modes and Timing" for details.
• Bit 0 – UCPOL0 - Clock Polarity
The UCPOL0 bit sets the polarity of the XCK0 clock. The combination of the UCPOL0
and UCPHA0 bit settings determine the timing of the data transfer. Refer to the section
"SPI Data Modes and Timing" for details.
• Bit 7 – RXC1 - USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when
the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is
disabled, the receive buffer will be flushed and consequently the RXC1 bit will become
zero. The RXC1 Flag can be used to generate a Receive Complete interrupt (see
description of the RXCIE1 bit).
• Bit 6 – TXC1 - USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted
out and there are no new data currently present in the transmit buffer (UDR1). The
TXC1 Flag bit is automatically cleared when a transmit complete interrupt is executed,
or it can be cleared by writing a one to its bit location. The TXC1 Flag can generate a
Transmit Complete interrupt (see description of the TXCIE1 bit).
• Bit 5 – UDRE1 - USART Data Register Empty
The UDRE1 Flag indicates if the transmit buffer (UDR1) is ready to receive new data. If
UDRE1 is one, the buffer is empty, and therefore ready to be written. The UDRE1 Flag
can generate a Data Register Empty interrupt (see description of the UDRIE1 bit).
UDRE1 is set after a reset to indicate that the Transmitter is ready.
• Bit 7 – RXCIE1 - RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC1 Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXC1 bit in UCSR1A is set.
Bit
NA ($C8)
Read/Write
Initial Value
Bit
NA ($C9)
Read/Write
Initial Value
RXCIE1
RXC1
RW
R
7
0
7
0
TXCIE1
TXC1
RW
RW
6
0
6
0
UDRIE1
UDRE1
RW
R
5
0
5
1
RXEN1
RW
4
4
0
TXEN1
RW
3
3
0
2
2
1
1
8266B-MCU Wireless-03/11
0
0
UCSR1A
UCSR1B