ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 78

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9-22. TX Power Ramping
9.6.3 Frame Buffer
9.6.3.1 Data Management
78
TRX_STATE
SLPTR
PA buffer
PA
M odulation
ATmega128RFA1
PLL_O N
0
2
When using an external RF front-end (refer to
required to adjust the startup time of the external PA relative to the internal building
blocks to optimize the overall PSD. This can be achieved using register bits
PA_BUF_LT and PA_LT of register PHY_TX_PWR.
The radio transceiver contains a 128 byte dual port SRAM. One port of the frame buffer
is directly connected to the controller I/O space. Therefore random access to single
frame bytes is possible. The other port connects to the internal transmitter and receiver
modules. Both ports are independent and simultaneously accessible for data
communication.
The Frame Buffer uses the controller I/O address space 0x180 to 0x1FF for RX and TX
operation of the radio transceiver and can keep one IEEE 802.15.4 RX or one TX frame
of maximum length at a time.
Frame Buffer access is only possible if the radio transceiver is enabled (PRTRX24 bit in
the Power Reduction Register PRR1 is not set) and not in SLEEP state.
Data in the Frame Buffer (received data or data to be transmitted) remain valid as long
as:
• No new frame or other data are written into the buffer;
• No new frame is received (in any BUSY_RX state);
• No state change into radio transceiver SLEEP state is made;
• No radio transceiver RESET (see bit TRXRST in
• Bit PRTRX24 in register
By default there is no protection of the Frame Buffer against overwriting. If a frame is
received during a Frame Buffer read access of a previously received frame, the stored
data might be overwritten.
Finally the application software should check the transferred frame data integrity by a
FCS check.
The state of the radio transceiver should be changed to PLL_ON state after reception to
protect the Frame Buffer content against overwriting with new, incoming frames. This
can be achieved by writing immediately the command PLL_ON to the TRX_CMD bits of
register TRX_STATE after receiving the frame indicated by a TRX24_RX_END
interrupt.
Register" on page
set;
4
6
170) or system reset took place;
8
"PRR1 – Power Reduction Register 1" on page 169
BU SY_TX
10
PA_BUF_LT
12
"RX/TX Indicator" on page
14
PA_LT
"TRXPR – Transceiver Pin
16
1 1
0
8266B-MCU Wireless-03/11
1
18
1
0 0
91) it may be
Length [µ s]
1
1
is not