ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 403

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.9.2 TWCR – TWI Control Register
8266B-MCU Wireless-03/11
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to
initiate a Master access by applying a START condition to the bus, to generate a
Receiver acknowledge, to generate a stop condition, and to control halting of the bus
while the data to be written to the bus are put into the TWDR. It also indicates a write
collision if data writing to TWDR is attempted while the register is inaccessible.
• Bit 7 – TWINT - TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects
application software response. If the I-bit in SREG and TWIE in TWCR are set, the
MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low
period is stretched. The TWINT Flag must be cleared by software by writing a logic one
to it. Note that this flag is not automatically cleared by hardware when executing the
interrupt routine. Also note that clearing this flag starts the operation of the TWI. So all
accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR) and TWI
Data Register (TWDR) must be complete before clearing this flag.
• Bit 6 – TWEA - TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is
written to one, the ACK pulse is generated on the TWI bus if the following conditions
are met: 1. The devices own slave address has been received; 2. A general call has
been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been
received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero,
the device can be virtually disconnected from the 2-wire Serial Bus temporarily.
Address recognition can then be resumed by writing the TWEA bit to one again.
• Bit 5 – TWSTA - TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the
2-wire Serial Bus. The TWI hardware checks if the bus is available and generates a
START condition on the bus if it is free. However, if the bus is not free, the TWI waits
until a STOP condition is detected and then generates a new START condition to claim
the bus Master status. TWSTA must be cleared by software when the START condition
has been transmitted.
• Bit 4 – TWSTO - TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-
wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is
cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover
from an error condition. This will not generate a STOP condition, but the TWI returns to
a well-defined not-addressed Slave mode and releases the SCL and SDA lines to a
high impedance state.
• Bit 3 – TWWC - TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register TWDR when
TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.
• Bit 2 – TWEN - TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is
written to one, the TWI takes control over the I/O ports connected to the SCL and SDA
Bit
NA ($BC)
Read/Write
Initial Value
TWINT
RW
7
0
TWEA
RW
6
0
TWSTA
RW
5
0
TWSTO
RW
4
0
TWWC
RW
3
0
ATmega128RFA1
TWEN
RW
2
0
Res
R
1
0
TWIE
RW
0
0
TWCR
403