ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 421

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.7.1 Analog Input Circuitry
8266B-MCU Wireless-03/11
3. If no other interrupts occur before the A/D conversion completes, the ADC interrupt
Note that the ADC will not be automatically turned off when entering other sleep modes
than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to
ADEN before entering such sleep modes to avoid excessive power consumption.
The analog input circuitry for single ended channels is illustrated in
An analog source applied to ADCn is subjected to the pin capacitance and input
leakage of that pin, regardless of whether that channel is selected as input for the ADC.
When the channel is selected, the source must drive the S/H capacitor through the
series resistance (combined resistance in the input path).
The ADC is optimized for analog signals having output impedance Z
approximately 3 k
negligible. If a source with higher impedance is used, the correct sampling time will
depend on how much time is needed to charge the S/H capacitor, which can vary
widely. The user is recommended to only use low impedance sources with slowly
varying signals, since this minimizes the required charge transfer to the S/H capacitor.
The required tracking time (input sampling switch closed) t
can be estimated to
for Z
guaranteed by the conversion logic. Based on the ADC clock frequency the bits
ADTHT[1:0] of register ADCSRC allow the adjustment of the tracking time to the user’s
requirements.
Tracking time requirements should also be considered for the differential mode. The
input signal is sampled by the gain amplifier. The value of the input capacitance C
depends on the selected gain (~7pF for 200x gain, <1pF otherwise). The tracking is
equal to 50% of the clock period of CK
frequency is required for input sources with high impedance.
Figure 27-11. Analog Input Circuitry
Signal components higher than the Nyquist frequency (f
either kind of channels, to avoid distortion from unpredictable signal convolution. The
user is advised to remove high frequency components with a low-pass filter before
applying the signals as inputs to the ADC.
will wake up the CPU and execute the ADC Conversion Complete interrupt routine.
If another interrupt wakes up the CPU before the A/D conversion is complete, that
interrupt will be executed, and an ADC Conversion Complete interrupt request will
be generated when the A/D conversion completes. The CPU will remain in active
mode until a new sleep command is executed.
OUT
> 3k
(worst case: maximum input step). A minimum tracking time of 500ns is
A D C n
or less. If such a source is used, the sampling time will be
t
DTRCK
=
(
I
I
IH
IL
Z
OUT
ADC2
/
k
Ω
. Hence in differential mode a slower clock
+
2000
2 k
)
ATmega128RFA1
⋅
. 0
V
ADC
097
A V D D
DTRCK
/2) should not be present for
/2
ns
C
S /H
to settle to within 1 LSB
= 1 4 p F
Figure 27-11
OUT
below.
421
S/H
of