ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 379

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.2.2 Electrical Interconnection
25.3 Data Transfer and Frame Format
25.3.1 Transferring Bits
25.3.2 START and STOP Conditions
8266B-MCU Wireless-03/11
The Power Reduction TWI bit, PRTWI bit in
page 168
As depicted in
supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices
are open-drain or open-collector. This implements a wired-AND function which is
essential to the operation of the interface. A low level on a TWI bus line is generated
when one or more TWI devices output a zero. A high level is output when all TWI
devices trim-state their outputs, allowing the pull-up resistors to pull the line high. Note
that all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus
capacitance limit of 400 pF and the 7-bit slave address space. A detailed specification
of the electrical characteristics of the TWI is given in
Characteristics" on page
one relevant for bus speeds below 100 kHz, and one valid for bus speeds up to 400
kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line.
The level of the data line must be stable when the clock line is high. The only exception
to this rule is for generating start and stop conditions.
Figure 25-2. Data Validity
SDA
The Master initiates and terminates a data transmission. The transmission is initiated
when the Master issues a START condition on the bus, and it is terminated when the
Master issues a STOP condition. Between a START and a STOP condition, the bus is
considered busy, and no other master should try to seize control of the bus. A special
case occurs when a new START condition is issued between a START and STOP
condition. This is referred to as a REPEATED START condition, and is used when the
Master wishes to initiate a new transfer without relinquishing control of the bus. After a
REPEATED START, the bus is considered busy until the next STOP. This is identical to
the START behavior, and therefore START is used to describe both START and
REPEATED START for the remainder of this datasheet, unless otherwise noted. As
depicted below, START and STOP conditions are signaled by changing the level of the
SDA line when the SCL line is high.
SCL
must be written to zero to enable the 2-wire Serial Interface.
Data Stable
Figure 25-1 on
Data Change
507. Two different sets of specifications are presented there,
page 378, both bus lines are connected to the positive
Data Stable
"PRR0 – Power Reduction Register0" on
ATmega128RFA1
"2-wire Serial Interface
379