ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 265

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.10 Timer/Counter Timing Diagrams
8266B-MCU Wireless-03/11
The definition of TOP with the ICRn Register works well when using fixed TOP values.
Combined with ICRn the OCRnA Register is available for generating a PWM output on
OCnA. However, if the base PWM frequency is actively changed by modifying the TOP
value, using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generating PWM
waveforms on the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-
inverted PWM. An inverted PWM output can be generated by setting the COMnx1:0 to
3 (see
pin if the data direction of the port pin is set to output (DDR_OCnx). The PWM
waveform is generated by setting (or clearing) the OCnx Register at the compare match
between OCRnx and TCNTn when the counter increments, and by clearing (or setting)
the OCnx Register at compare match between OCRnx and TCNTn when the counter
decrements. The PWM frequency of the output f
frequency correct PWM can be calculated with the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
set to high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and
COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set and when the OCRnx Register is updated with the
OCRnx buffer value (only for modes utilizing double buffering). Figure 18-10 shows a
timing diagram for the setting of OCFnx.
Figure 18-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
TCNTn
OCRnx
OCFnx
(clk
clk
clk
I/O
Table 18-4 on
I/O
Tn
/1)
OCRnx - 1
page 257). The actual OCnx value will only be visible at the port
f
OCnxPFCPWM
OCRnx
OCRnx Value
=
2
⋅
f
N
clk
⋅
_
TOP
OCnxPFCPWM
I
ATmega128RFA1
/
O
OCRnx + 1
)
when using phase and
OCRnx + 2
Tn
) is therefore
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