ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 32

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3 Transceiver to Microcontroller Interface
9.3.1 Transceiver Configuration and Data Access
9.3.1.1 Register Access
32
ATmega128RFA1
The received RF signal at pins RFN and RFP is differentially fed through the low-noise
amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the
integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the
succeeding analog-to-digital converter (RX ADC) and generates a digital RSSI signal.
The RX ADC output signal is sampled by the digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping
and 32-length block coding (spreading) according to
101. The modulation signal is generated in the digital transmitter (TX BBP) and applied
to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation
required for demodulation of O-QPSK signals. The frequency-modulated signal is fed to
the power amplifier (PA).
A differential pin pair DIG3/DIG4 can be enabled to control an external RF front-end.
The two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and
digital 1.8V supply.
An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be
transmitted or received.
The configuration of the reading and writing of the Frame Buffer is controlled via the
microcontroller interface.
The transceiver further contains comprehensive hardware-MAC support (Extended
Operating Mode) and a security engine (AES) to improve the overall system power
efficiency and timing. The 128-bit AES engine can be accessed in parallel to all PHY
operational transactions and states using the microcontroller interface, except during
transceiver power down state.
For applications not necessarily targeting IEEE 802.15.4 compliant networks, the radio
transceiver also supports alternative data rates up to 2 Mb/s.
For long-range applications or to improve the reliability of an RF connection the RF
performance can further be improved by using an external RF front-end or Antenna
Diversity. Both operation modes are supported by the radio transceiver with dedicated
control pins without the interaction of the microcontroller.
Additional features of the Extended Feature Set, see section
Extended Feature Set" on page
radio transceiver and microcontroller.
This section describes the internal Interface between the transceiver module and the
microcontroller. Unlike all other AVR I/O modules, the transceiver module can operate
asynchronously to the controller. The transceiver requires an accurate 16MHz crystal
clock for operation, but the controller can run at any frequency within its operating limits.
Note that the on-chip debug system (see section
page
All transceiver registers are mapped into I/O space of the controller. Due to the
asynchronous interface a register access can take up to three transceiver clock cycles.
Depending on the controller clock speed, program execution wait cycles are generated.
439) must be disabled for the best RF performance of the radio transceiver.
86, are provided to simplify the interaction between
"Using the On-chip Debug System" on
[1] on page 101
"Radio Transceiver
8266B-MCU Wireless-03/11
and
[2] on page