ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 166

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.5.4 Low Leakage Voltage Regulator (LLVREG)
12.5.5 Low Leakage Voltage Regulator Control
166
ATmega128RFA1
The main digital voltage regulator (DVREG) will be switched off during the
DEEP_SLEEP modes “power-down” and “power-save”. The Low Leakage Voltage
Regulator will then keep the digital supply voltage to provide data retention. No
application software control is required.
During the active power states, when the main voltage regulator supplies the chip, the
Low Leakage Voltage Regulator is digitally calibrated. Its output voltage is adjusted to
match the output voltage of the main regulator. This fixed calibration result is stored and
used when the chip enters a power-down state where the main regulator is switched off.
Because the calibration setting is fixed, temperature and load current variations during
the following DEEP_SLEEP period are not regulated out. Thus the output voltage may
drift away from the target value. However the design guarantees that for allowed
operating conditions the output voltage will stay within valid limits. After every wake-up
a new calibration cycle is initiated.
The output driving capability of the Low Leakage Voltage Regulator is limited. Its main
purpose is to provide the leakage current of the connected analog and digital blocks.
At least one full calibration cycle of the Low Leakage Voltage Regulator has to be
completed before the power-chain can be disabled. Therefore if the CPU uses one of
the DEEP_SLEEP modes “power down” or “power save”, the power-chain is not
disabled before the Low Leakage Voltage Regulator completed this first calibration
cycle.
By default the LLVREG automatically starts the calibration after finishing the power-on
reset and the wake-up/start-up procedures (see section
Regulator Control" below
Regulator).
The three register LLCR, LLDRL and LLDRH allow the software to monitor the
calibration process and to modify or correct the calibration results. The automatic
calibration is the normal operation mode. It is an internal process that does not require
any software interaction. Nevertheless the calibration is transparent for the user through
LLCR, LLDRL and LLDRH (control and data register respectively).
The register access requires a minimum system clock of at least the output frequency
of the 128 kHz RC oscillator. The register access will not work if the system clock is
slower. See chapter
set the system clock frequency.
Before the device can enter the sleep mode “power down” or “power save” the first
calibration cycle of the Low Leakage Voltage Regulator must be completed to get valid
data in LLDRL and LLDRH. The cycle time t
temperature, manufacturing process and the frequency of the 128 kHz RC oscillator
(independent of the Watchdog setting).
Systems that require very short power-up times may temporarily disable the calibration
process by setting bit LLENCAL to 0. After disabling the calibration the register values
Notes:
1. The LLVREG calibration will be inaccurate at a DEVDD supply voltage of
1.8V or lower. Therefore when operating the device at 1.8V the LLVREG
calibration should be disabled and the register values of LLDRL and
LLDRH should be set to 0x06 and 0x0f, respectively.
System Clock and Clock Options on page 148
for a detailed description of the Low Leakage Voltage
LLVREG_CALIB
is not fixed. It depends on the
"Low Leakage Voltage
for details on how to
8266B-MCU Wireless-03/11