ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 105

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.6 TRX_STATE – Transceiver State Control Register
8266B-MCU Wireless-03/11
The states of the radio transceiver are controlled via register TRX_STATE using
register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status
or result of an Extended Operating Mode transaction. A successful state transition shall
be confirmed by reading register bits TRX_STATUS. This register is used for both Basic
and Extended Operating Mode.
• Bit 7:5 – TRAC_STATUS2:0 - Transaction Status
The status of the RX_AACK and TX_ARET procedure is indicated by register bits
TRAC_STATUS. TRAC_STATUS is only valid in Extended Operating Modes. Details of
the algorithm and a description of the status information are given in the RX_AACK_ON
and TX_ARET_ON sections of the data-sheet. Even though the reset value for register
bits TRAC_STATUS is 0, the RX_AACK and TX_ARET procedures set the register bits
to TRAC_STATUS = 7 (INVALID) when it is started. Not all status values are used in
both
SUCCESS_DATA_PENDING indicates a successful reception of an ACK frame with
frame pending bit set to 1. In RX_AACK the status SUCCESS_WAIT_FOR_ACK
indicates an ACK frame is about to sent in RX_AACK slotted acknowledgment. Slotted
acknowledgment operation must be enabled with the SLOTTED_OPERATION bit of
register XAH_CTRL_0. The application software must set the SLPTR bit of register
TRXPWR at the next back-off slot boundary in order to initiate a transmission of the
Bit
NA ($142)
Read/Write
Initial Value
Bit
NA ($142)
Read/Write
Initial Value
Register Bits
RX_AACK
TRAC_STATUS2 TRAC_STATUS1 TRAC_STATUS0
TRX_CMD3
RW
R
7
0
3
0
and
TX_ARET
TRX_CMD2
RW
R
6
0
2
0
Value
0x01
0x02
0x06
0x08
0x09
0x0F
0x11
0x12
0x16
0x19
0x1F
transactions.
TRX_CMD1
Description
BUSY_RX
BUSY_TX
RX_ON
TRX_OFF
PLL_ON
SLEEP
BUSY_RX_AACK
BUSY_TX_ARET
RX_AACK_ON
TX_ARET_ON
STATE_TRANSITION_IN_PROGRESS
RW
R
5
0
1
0
ATmega128RFA1
In
TRX_CMD4
TRX_CMD0
RW
RW
4
0
0
0
TX_ARET
TRX_STATE
TRX_STATE
the
status
105