ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 172

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.6.7 DRTRAM1 – Data Retention Configuration Register of SRAM 1
12.6.8 DRTRAM2 – Data Retention Configuration Register of SRAM 2
172
ATmega128RFA1
The DRTRAM1 register controls the behavior of SRAM block 1 in the power-states
"power-save" and "power-down". To prevent any data loss the SRAM will not
completely disconnected from the power supply. Reserved bits will be overwritten
during chip reset by the factory calibration and should not be modified.
• Bit 7:6 – Res1:0 - Reserved
• Bit 5 – DRTSWOK - DRT Switch OK
This bit indicates the status of the SRAM power-switch. A logical one indicates that the
SRAM supply voltage is fully available and the memory may be accessed normally.
• Bit 4 – ENDRT - Enable SRAM Data Retention
During "Deep-Sleep" each SRAM block will either be switched off or provides data
retention of its memory content. This bit must set to one if data retention mode should
be used. Otherwise the SRAM is switched off (disconnected from the power supply)
and all its data are lost.
• Bit 3:0 – Resx3:0 - Reserved
The DRTRAM2 register controls the behavior of SRAM block 2 in the power-states
"power-save" and "power-down". To prevent any data loss the SRAM will not
completely disconnected from the power supply. Reserved bits will be overwritten
during chip reset by the factory calibration and should not be modified.
• Bit 7 – Resx7 - Reserved
• Bit 6 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 5 – DRTSWOK - DRT Switch OK
This bit indicates the status of the SRAM power-switch. A logical one indicates that the
SRAM supply voltage is fully available and the memory may be accessed normally.
• Bit 4 – ENDRT - Enable SRAM Data Retention
During "Deep-Sleep" each SRAM block will either be switched off or provides data
retention of its memory content. This bit must set to one if data retention mode should
be used. Otherwise the SRAM is switched off (disconnected from the power supply)
and all its data are lost.
• Bit 3:0 – Resx3:0 - Reserved
Bit
NA ($134)
Read/Write
Initial Value
Bit
NA ($133)
Read/Write
Initial Value
Resx7
Res1
RW
R
7
0
7
0
Res0
Res
R
R
6
0
6
0
DRTSWOK ENDRT
DRTSWOK ENDRT
R
R
5
0
5
0
RW
RW
4
0
4
0
Resx3
Resx3
RW
RW
3
0
3
0
Resx2
Resx2
RW
RW
2
0
2
0
Resx1
Resx1
RW
RW
1
0
1
0
8266B-MCU Wireless-03/11
Resx0
Resx0
RW
RW
0
0
0
0
DRTRAM1
DRTRAM2