ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 33

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.1.2 Frame Buffer Access
9.3.1.3 Transceiver Pin Register TRXPR
8266B-MCU Wireless-03/11
That means if the controller runs with about 16MHz or faster, at least three wait cycles
are generated, but if the controller runs with about 4MHz, no wait cycles are inserted. A
register access is only possible, if the transceiver clock is available. Therefore the
transceiver must be enabled (PRR1 Register) and not in SLEEP state.
The 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one
IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed
description of the Frame Buffer can be found in section
introduction to the IEEE 802.15.4 frame format can be found in section
IEEE 802.15.4-2006 Frame Format" on page
The Frame Buffer is located within the controller I/O address space above of the
transceiver register set. The first byte of the Frame Buffer can be accessed with the
symbolical address TRXFBST and the last byte can be accessed with the symbolical
address TRXFBEND. Random access to single frame bytes is possible with “TRXFBST
+ byte index” or “TRXFBEND – byte index”. In contrast to the transceiver register
access, the Frame Buffer allows single cycle read/write operations for all controller
clock speeds.
The content of the Frame Buffer is only overwritten by a new received frame or a Frame
Buffer write access.
The Frame Buffer usage is different between received and transmitted frames.
Therefore it is not possible to retransmit a received frame without modifying the frame
buffer.
On received frames, the frame length byte is not stored in the Frame Buffer, but can be
accessed over the TST_FRAME_LENGTH register. During frame receive, the Link
Quality Indication (LQI) value (refer to
appended to the frame data in the Frame Buffer.
For frame transmission, the first byte of the Frame Buffer must contain the frame length
information followed by the frame data. The TST_FRAME_LENGTH register does not
need to be written in this case.
A detailed description of the Frame Buffer usage for receive and transmit frames can be
found in
Notes:
1. The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by
2. To avoid overwriting during receive, Dynamic Frame Buffer Protection can be enabled. For
3. It is not possible to retransmit received frames without inserting the frame length information at
4. For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode
The Transceiver Pin Register TRXPR is located in the Controller clock domain and is
accessible even if the transceiver is in sleep state. This register provides access to the
pin functionality, known from the RF231 devices (two chip solution).
new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no
frame was received in the meanwhile.
details about this feature refer to section
the beginning of the Frame Buffer. That requires a complete read out of the received frame
and rewriting the modified frame to the Frame Buffer.
(TX_ARET) refer to section
Retry" on page
Figure 9-31 on page
58.
"TX_ARET_ON – Transmit with Automatic Retry and CSMA-CA
79.
"Dynamic Frame Buffer Protection" on page
"Link Quality Indication (LQI)" on page 73
62.
ATmega128RFA1
"Frame Buffer" on page
"Introduction –
92.
78. An
) is
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