ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 135

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4 Symbol Counter (32 bit, SCCNT)
10.5 Symbol Counter SFD Timestamp Register (32 bit, SCTSR, Read Only)
10.6 Symbol Counter Beacon Timestamp Register (32 bit, SCBTSR)
8266B-MCU Wireless-03/11
The symbol counter is a 32 bit counter which can be sourced by a 62.5 kHz clock,
derived from the 16 MHz system clock or from the RTC (32.768 kHz). If sourced by the
RTC, a special control circuitry ensures that the counter error does not exceed one
symbol period.
The symbol counter can be set or read from the controller. Reading must start with the
least significant byte. If the least significant byte is accessed, all 32 bit of the counter
are captured. A read access to SCCNTLL requires a maximum of three AVR clocks.
Reading the upper three bytes of the counter requires two CPU clock cycles for each
byte.
Writing to the counter should start with the most significant byte. Writing the least
significant byte initiates the counter update and the new 32 bit counter value is loaded
into the counter with the next available counter clock edge. This can take up to 16 µs
beginning from the low byte write operation, if the counter is sourced by the RTC.
If the counter clock is derived from the 16 MHz clock system, the new counter value is
stored immediately.
During the counter update cycle, the counter busy flag SCBSY in the SCSR register is
set to “1”. As long as this bit is “1”, no further read/write access to the counter should be
initiated. The same applies if the AVR is forced to any sleep mode with disabled AVR
clock, right after writing to the SCCNT register. If the counter busy flag is not checked
before going to sleep, it is possible that the counter register is not updated correctly.
The symbol counter overflow is indicated by a overflow interrupt. The interrupt is
generated when the counter turns from 0xFFFFFFFF to 0x00000000.
The SFD timestamp register stores the symbol counter value at the time, the SFD has
been detected. The Register value becomes valid if a valid frame length byte (frame
length > 0) has been detected, but it is not checked if the received frame is valid (CRC
check). Timestamping must be enabled in the control register (Bit SCTSE of Register
SCCR0). A read access to SCTSRLL requires a maximum of three AVR clocks.
Reading the upper three bytes of the timestamp requires two CPU clock cycles for each
byte.
Note that there is no separate interrupt provided for timestamping. Instead the
TRX24_RX_START interrupt can be used (see
on page
If timestamping is enabled in the SCCR register, the beacon timestamp register is
updated with the SFD timestamp at the end of the received frame, if the received frame
was a beacon frame with valid FCS and:
or
PAN_ID_0 and PAN_ID_1 are register of the radio transceiver, see
Beacon timestamps can also be generated manually. Writing “1” to SCMBTS of
Register SCCR0 captures the current symbol counter value and stores it in the beacon
timestamp register. The bit is cleared automatically afterwards.
Transceiver Personal Area Network ID Register (Low
•
•
212).
Source PAN identifier == {PAN_ID_1, PAN_ID_0}
{PAN_ID_1, PAN_ID_0} == 0xFFFF
"Interrupt Vectors in ATmega128RFA1"
ATmega128RFA1
Byte)"
on page
125.
"PAN_ID_0 –
135