ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 89

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.8.2.5 High Data Rate Mode Options
Figure 9-32. High Data Rate AACK Timing
9.8.3 Antenna Diversity
9.8.3.1 Overview
8266B-MCU Wireless-03/11
AACK_ACK_TIME = 0
AACK_ACK_TIME = 1
0
192
Receiver Sensitivity Control
The different data rates between PPDU header (SHR and PHR) and PHY payload
(PSDU) cause a different sensitivity between header and payload. This can be adjusted
by defining sensitivity threshold levels of the receiver. The receiver does not receive
frames with an RSSI level below the defined sensitivity threshold level (register bits
RX_PDT_LEVEL > 0). Under these operating conditions the receiver current
consumption is reduced by 500 µA (refer to chapter
Specifications" on page
A description of the settings to control the sensitivity threshold with register RX_SYN
can be found in section
on page
Reduced Acknowledgment Timing
On higher data rates the IEEE 802.15.4 compliant acknowledgment frame response
time of 192 µs significantly reduces the effective data rate of the network. To minimize
this influence in Extended Operating Mode RX_AACK (see section
Receive with Automatic ACK" on page
can be reduced to 32 µs.
acknowledgement of a frame with a data rate of 2000 kb/s and a PSDU length of 80
symbols. The PSDU length of the acknowledgment frame is 5 octets according to
IEEE 802.15.4.
The acknowledgment time is reduced from 192 µs to 32 s if bit AACK_ACK_TIME of
register XAH_CTRL_1 is set.
The main features of the Antenna Diversity implementation are:
• Improves signal path robustness between nodes;
• Self-contained antenna diversity algorithm of the radio transceiver;
• Direct register based antenna selection;
The receive signal strength may vary and affect the link quality even for small changes
of the antenna location due to multipath propagation effects between network nodes.
These fading effects can result in an increased error floor or loss of the connection
between devices.
Antenna Diversity can be applied to reduce the effects of multipath propagation and
fading hence improving the reliability of a RF connection between network nodes.
PSDU: 80 octets
PSDU: 80 octets
120.
513).
"RX_SYN – Transceiver Receiver Sensitivity Control Register"
Figure 9-32 below
512
544
192 µs
32 µs
47), the acknowledgment frame response time
704
illustrates an example for a reception and
ACK
ATmega128RFA1
916
ACK
"Current Consumption
"RX_AACK_ON –
time [µs]
89