ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 269

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.11.2 TCCR1B – Timer/Counter1 Control Register B
8266B-MCU Wireless-03/11
• Bit 7 – ICNC1 - Input Capture 1 Noise Canceller
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise
Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter
function requires four successive equal valued samples of the ICP1 pin for changing its
output. The input capture is therefore delayed by four Oscillator cycles when the noise
canceler is enabled.
• Bit 6 – ICES1 - Input Capture 1 Edge Select
This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a
capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used
as trigger. When the ICES1 bit is written to one, a rising (positive) edge will trigger the
capture. When a capture is triggered according to the ICES1 setting, the counter value
is copied into the Input Capture Register (ICR1). The event will also set the Input
Capture Flag (ICF1). This can be used to cause an Input Capture Interrupt, if this
interrupt is enabled. When the ICR1 is used as TOP value (see description of the
WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is
disconnected and consequently the input capture function is disabled.
• Bit 5 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 4:3 – WGM11:10 - Waveform Generation Mode
Bit
NA ($81)
Read/Write
Initial Value
Register Bits
ICNC1
RW
7
0
ICES1
RW
6
0
Res
R
5
0
Value
0xA
0xB
0xC
0xD
0xE
0xF
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
WGM13
RW
4
0
WGM12
Description
PWM, phase correct, 9-bit
PWM, phase correct, 10-bit
CTC, TOP = OCRnA
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
PWM, Phase and frequency correct, TOP =
ICRn
PWM, Phase and frequency correct, TOP =
OCRnA
PWM, Phase correct, TOP = ICRn
PWM, Phase correct, TOP = OCRnA
CTC, TOP = OCRnA
Reserved
Fast PWM, TOP = ICRn
Fast PWM, TOP = OCRnA
RW
3
0
ATmega128RFA1
CS12
RW
2
0
CS11
RW
1
0
CS10
RW
0
0
TCCR1B
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