ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 342

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.3.1 Internal Clock Generation – The Baud Rate Generator
342
ATmega128RFA1
Figure 22-2 on
Figure 23-2. Clock Generation Logic, Block Diagram
Signal description:
txclk
rxclk
xcki
xcko
f
Internal clock generation is used for the asynchronous and the synchronous master
modes of operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it
function as a programmable prescaler or baud rate generator. The down-counter,
running at system clock (f
has counted down to zero or when the UBRRLn register is written. A clock is generated
each time the counter reaches zero. This clock is the baud rate generator clock output
(= f
8 or 16 depending on mode. The baud rate generator output is used directly by the
receiver’s clock and data recovery units. However, the recovery units use a state
machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
Table 23-1 below
and for calculating the UBRRn value for each mode of operation using an internally
generated clock source.
Table 23-1. Equations for Calculating Baud Rate Register Setting
OSC
Operating Mode
Asynchronous Normal Mode
(U2Xn = 0)
Asynchronous Double Speed
Mode (U2Xn = 1)
OSC
/(UBRRn+1)). The transmitter divides the baud rate generator clock output by 2,
Transmitter clock (internal signal).
Receiver base clock (internal signal).
Input from XCK pin (internal signal). Used for synchronous slave operation.
Clock output to XCK pin (internal signal). Used for synchronous master
operation.
System clock frequency.
page 332 shows a block diagram of the clock generation logic.
contains equations for calculating the baud rate (in bits per second)
OSC
), is loaded with the UBRRn value each time the counter
Equation for Calculating
Baud Rate
BAUD
BAUD
=
=
(1)
16
( 8
UBRRn
(
UBRRn
f
f
OSC
OSC
+
+
) 1
) 1
Figure 22-2 on
Equation for Calculating
UBRR Value
UBRRn
UBRRn
8266B-MCU Wireless-03/11
=
=
16
8
BAUD
f
BAUD
f
page 332.
OSC
OSC
−
−
1
1