ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 136
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 136 of 555
- Download datasheet (6Mb)
10.7 Compare Unit (3x 32 bit, SCOCR1, SCOCR2, SCOCR3)
10.8 Interrupt Control Registers
10.9 Backoff Slot Counter
10.10 Symbol Counter Usage
10.10.1 SFD and Beacon Timestamp Generation
136
ATmega128RFA1
It is also possible to manually set the register in order to provide a distinct starting value
for the relative compare modes (see next section).
The compare unit contains 3 independent 32 bit compare modules and is used to
compare the current counter value with the value stored in the compare register, and
optionally the beacon timestamp register. There are two possible modes available
which can be selected separately for all three compare modules:
1. Absolute Compare: In this mode the value stored in the compare register is
compared directly with the symbol counter value (SCCNT == SCOCRx). If the values
are equal an interrupt is generated.
2. Relative Compare: This mode allows the compare between the current symbol
counter value and the compare value plus the beacon timestamp value (SCCNT ==
SCBTSR + SCOCRx). This mode can be used to generate an interrupt at a time offset
relative to the value stored in the beacon timestamp register.
Note that a beacon timestamp is valid after a valid FCS. The relative compare must
exceed the beacon length, otherwise no relative compare interrupt will occur.
The interrupt status and mask registers control the interrupt generation. Each interrupt
can be enabled in SCIRQM (Symbol Counter IRQ Mask Register). If an interrupt
occurs, the appropriate interrupt flag within the interrupt status register is set regardless
of the interrupt mask register setting. If the appropriate interrupt is enabled, an interrupt
is generated.
The interrupt flags can be cleared either by:
All Interrupts can be used to wakeup the controller from any sleep state.
The backoff slot counter can be used to provide accurate MAC protocol timing. The
counter is sourced by the transceiver clock and works only if the transceiver clock is
running. If the transceiver is disabled or in sleep mode the counter is also disabled.
The counter generates periodic Interrupts every 20 symbols, i.e. every 320 µs.
The SFD timestamp register is updated with the symbol counter value at the time the
SFD value has been received completely. For an incoming frame, the register is valid
after the RX_START IRQ was issued until the next RX_START IRQ. SFD timestamps
are generated for all incoming frames with valid SFD and length field even if the PSDU
is corrupted (invalid FCS).
1. Entering the respective interrupt handler, or
2. Writing “one” to the according interrupt flag in the interrupt status register.
8266B-MCU Wireless-03/11
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