ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 114

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.17 ANT_DIV – Antenna Diversity Control Register
114
ATmega128RFA1
Table 9-46 OQPSK_DATA_RATE Register Bits
This register controls the Antenna Diversity.
• Bit 7 – ANT_SEL - Antenna Diversity Antenna Status
This register bit signals the currently selected antenna path. The selection may be
based either on the last antenna diversity cycle (ANT_DIV_EN = 1) or on the content of
register bits ANT_CTRL.
Table 9-47 ANT_SEL Register Bits
• Bit 6:4 – Res2:0 - Reserved
• Bit 3 – ANT_DIV_EN - Enable Antenna Diversity
If this register bit is set the Antenna Diversity algorithm is enabled. On reception of a
frame the algorithm selects an antenna autonomously during SHR search. This
selection is kept until
1. a new SHR search starts or
2. receive states are left or
3. a manually programming of bits ANT_CTRL occurred. If ANT_DIV_EN = 1 the bit
ANT_EXT_SW_EN shall also be set to 1.
Table 9-48 ANT_DIV_EN Register Bits
• Bit 2 – ANT_EXT_SW_EN - Enable External Antenna Switch Control
If enabled, pin DIG1 and pin DIG2 become output pins and provide a differential control
signal for an external Antenna Diversity switch. The selection of a specific antenna is
done either by the automatic Antenna Diversity algorithm (ANT_DIV_EN = 1) or
Bit
NA ($14D)
Read/Write
Initial Value
Bit
NA ($14D)
Read/Write
Initial Value
Register Bits
OQPSK_DATA_RATE1:0
Register Bits
ANT_SEL
Register Bits
ANT_DIV_EN
ANT_DIV_EN
ANT_SEL
RW
R
7
0
3
0
ANT_EXT_SW_EN
Res2
RW
R
6
0
2
0
Value
Value
Value
0
1
2
3
0
1
0
1
ANT_CTRL1
Res1
Description
250 kb/s (IEEE 802.15.4 compliant)
500 kb/s
1000 kb/s
2000 kb/s
Description
Antenna 0
Antenna 1
Description
Antenna Diversity algorithm disabled
Antenna Diversity algorithm enabled
R
5
0
RW
1
1
ANT_CTRL0
Res0
R
4
0
RW
0
1
8266B-MCU Wireless-03/11
ANT_DIV
ANT_DIV