ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 113

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.15 SFD_VALUE – Start of Frame Delimiter Value Register
9.12.16 TRX_CTRL_2 – Transceiver Control Register 2
8266B-MCU Wireless-03/11
This register contains the one octet start-of-frame delimiter (SFD) to synchronize to a
received frame. The lower 4 bits must not be all zero to avoid decoding conflicts.
• Bit 7:0 – SFD_VALUE7:0 - Start of Frame Delimiter Value
For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default
value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value
can be changed to any other value. If enabled a RX_START interrupt is issued only if
the received SFD matches the register content of SFD_VALUE and a valid PHR is
received.
Table 9-45 SFD_VALUE Register Bits
This register controls the data rate setting of the radio transceiver.
• Bit 7 – RX_SAFE_MODE - RX Safe Mode
If this bit is set, the next received frame will be protected and not overwritten by
following frames. Set this bit to 0 to release the buffer (and set it again for further
protection).
• Bit 6:2 – Res4:0 - Reserved
• Bit 1:0 – OQPSK_DATA_RATE1:0 - Data Rate Selection
A write access to these register bits sets the OQPSK PSDU data rate used by the radio
transceiver. The reset value OQPSK_DATA_RATE = 0 is the PSDU data rate according
to IEEE 802.15.4. All other values are used in High Data Rate Modes.
Bit
NA ($14B)
Read/Write
Initial Value
Bit
NA ($14C)
Read/Write
Initial Value
Bit
NA ($14C)
Read/Write
Initial Value
Register Bits
Register Bits
SFD_VALUE7:0
RX_SAFE_MODE
RW
7
1
Res1
R
3
0
RW
7
0
RW
6
0
Res0
R
RW
2
0
5
1
Res4
R
6
0
SFD_VALUE7:0
Value
Value
OQPSK_DATA_RATE1 OQPSK_DATA_RATE0
RW
0xA7
4
0
RW
RW
1
0
3
0
Description
Antenna Diversity operation
Description
IEEE 802.15.4 compliant value of the SFD
Res3
R
5
0
RW
2
1
ATmega128RFA1
RW
1
1
Res2
RW
R
0
0
4
0
RW
0
1
SFD_VALUE
TRX_CTRL_2
TRX_CTRL_2
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