ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 229

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.5 Output Compare Unit
8266B-MCU Wireless-03/11
Figure 17-2. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented or
decremented at each timer clock (clk
internal clock source selected by the Clock Select bits (CS02:0). When no clock source
is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be
accessed by the CPU regardless of whether clk
overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits
located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in
the Timer/Counter Control Register B (TCCR0B). There are close connections between
how the counter behaves (counts) and how waveforms are generated on the Output
Compare outputs OC0A and OC0B. For more details about advanced counting
sequences and waveform generation, see
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation
selected by the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare
Registers (OCR0A and OCR0B). The comparator signals a match whenever TCNT0
equals OCR0A or OCR0B. A match will set the Output Compare Flag (OCF0A or
OCF0B) at the next clock cycle of the timer. If the corresponding interrupt is enabled,
the Output Compare Flag generates an Output Compare interrupt. The Output
Compare Flag is automatically cleared when the interrupt is executed. The flag can
alternatively be software-cleared by writing a logical one to its I/O bit location. The
Waveform Generator uses the match signal to generate an output according to the
operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits.
The MAX and BOTTOM signals are used by the Waveform Generator for handling the
special cases of the extreme values in some modes of operation (refer to
Operation" on
count
direction
clear
clk
top
bottom
Tn
DATA BUS
page 233).
TCNTn
Increment or decrement TCNT0 by 1;
Select between increment and decrement;
Clear TCNT0 (set all bits to zero);
Timer/Counter clock referred to as clk
Signalize that TCNT0 has reached maximum value;
Signalize that TCNT0 has reached minimum value (zero);
direction
count
clear
T0
bottom
). clk
"Modes of Operation" on
Control Logic
T0
T0
can be generated from an external or
is present or not. A CPU write access
top
ATmega128RFA1
TOVn
(Int.Req.)
clk
T0
Tn
in the following text;
Clock Select
( From Prescaler )
Detector
Edge
page 233.
"Modes of
Tn
229