ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 383
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 383 of 555
- Download datasheet (6Mb)
25.5 Overview of the TWI Module
8266B-MCU Wireless-03/11
must contain the same number of data packets, otherwise the result of the arbitration is
undefined.
Figure 25-8. Arbitration Between Two Masters
Synchronized
The TWI module is comprised of several sub-modules, as shown in
All registers drawn in a thick line are accessible through the AVR data bus.
Figure 25-9. Overview of the TWI Module
SCL Line
SDA from
SDA from
Master A
Master B
SDA Line
Slew-rate
Address Match Unit
Arbitration detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
START
(TWAR)
Spike
Filter
Bus Interface Unit
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
SDA
Status Register
Ack
Spike
Filter
(TWSR)
Arbitration, SDA
Master A Loses
State Machine and
Control Unit
Status control
ATmega128RFA1
A
Bit Rate Generator
SDA
Control Register
Bit Rate Register
Prescaler
(TWCR)
(TWBR)
Figure 25-9
below.
383
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