ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 552

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

552
ATmega128RFA1
28 JTAG Interface and On-chip Debug System............................... 436
29 IEEE 1149.1 (JTAG) Boundary-scan............................................ 442
30 Boot Loader Support – Read-While-Write Self-Programming... 451
31 Memory Programming.................................................................. 465
27.6 Changing Channel or Reference Selection...................................................... 418
27.7 ADC Noise Canceller ....................................................................................... 420
27.8 ADC Conversion Result ................................................................................... 424
27.9 Internal Temperature Measurement................................................................. 426
27.10 SRAM DRT Voltage Measurement ................................................................ 427
27.11 Register Description ....................................................................................... 428
28.1 Features ........................................................................................................... 436
28.2 Overview........................................................................................................... 436
28.3 TAP - Test Access Port .................................................................................... 437
28.4 TAP Controller .................................................................................................. 438
28.5 Using the Boundary-scan Chain....................................................................... 439
28.6 Using the On-chip Debug System .................................................................... 439
28.7 On-chip Debug Specific JTAG Instructions ...................................................... 440
28.8 Using the JTAG Programming Capabilities...................................................... 440
28.9 Bibliography...................................................................................................... 441
28.10 On-chip Debug Related Register in I/O Memory............................................ 441
29.1 Features ........................................................................................................... 442
29.2 System Overview ............................................................................................. 442
29.3 Data Registers.................................................................................................. 442
29.4 Boundary-scan Specific JTAG Instructions ...................................................... 444
29.5 Boundary-scan Chain....................................................................................... 445
29.6 Boundary-scan Related Register in I/O Memory.............................................. 448
29.7 Boundary-scan Description Language Files .................................................... 449
29.8 ATmega128RFA1 Boundary-scan Order ......................................................... 449
30.1 Features ........................................................................................................... 451
30.2 Application and Boot Loader Flash Sections ................................................... 451
30.3 Read-While-Write and No Read-While-Write Flash Sections .......................... 452
30.4 Boot Loader Lock Bits ...................................................................................... 454
30.5 Addressing the Flash During Self-Programming.............................................. 454
30.6 Self-Programming the Flash............................................................................. 455
30.7 Register Description ......................................................................................... 462
31.1 Program And Data Memory Lock Bits .............................................................. 465
8266B-MCU Wireless-03/11