ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 175

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.6.12 LLDRL – Low Leakage Voltage Regulator Data Register (Low-Byte)
12.6.13 DPDS0 – Port Driver Strength Register 0
8266B-MCU Wireless-03/11
The low-byte of the calibration data can be accessed through this register. Write access
is only enabled when the bit LLENCAL of the LLCR register is 0. Then the data bits
LLDRL3:0 directly control the output voltage of the low-leakage voltage regulator.
Higher numbers generate lower voltages. The contents of this register is meaningless
when the bit LLSHORT of the LLCR register is 1. If the bit LLENCAL is 1 then the
results of the automatic calibration are stored.
• Bit 7:4 – Res3:0 - Reserved
These bits are reserved for future use.
• Bit 3:0 – LLDRL3:0 - Low-Byte Data Register Bits
Value of the low-byte calibration result
Table 12-6 LLDRL Register Bits
The output driver strength can be set individually for each digital I/O port. The following
tables show output current levels for a typical supply voltage of DEVDD = 3.3V. Refer to
section "Electrical Characteristics" for details.
• Bit 7:6 – PFDRV1:0 - Driver Strength Port F
Table 12-7 PFDRV Register Bits
• Bit 5:4 – PEDRV1:0 - Driver Strength Port E
Table 12-8 PEDRV Register Bits
Bit
NA ($130)
Read/Write
Initial Value
Bit
NA ($136)
Read/Write
Initial Value
Register Bits
LLDRL3:0
Register Bits
PFDRV1:0
Register Bits
PEDRV1:0
PFDRV1 PFDRV0 PEDRV1 PEDRV0 PDDRV1 PDDRV0 PBDRV1 PBDRV0
Res3
RW
R
7
0
7
0
Res2
RW
R
6
0
6
0
Res1
RW
R
5
0
5
0
Value
Value
Value
0x00
0x08
0
1
2
3
0
Res0
RW
R
4
0
4
0
LLDRL3 LLDRL2 LLDRL1 LLDRL0
Description
Calibration limit for fast process corner/high
output voltage
Calibration limit for slow process corner/low
output voltage
Description
2 mA
4 mA
6 mA
8 mA
Description
2 mA
RW
RW
3
0
3
0
ATmega128RFA1
RW
RW
2
0
2
0
RW
RW
1
0
1
0
RW
RW
0
0
0
0
LLDRL
DPDS0
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