ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 370

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.2.1 Clock Generation
24.3 SPI Data Modes and Timing
370
ATmega128RFA1
The Clock Generation logic generates the base clock for the Transmitter and Receiver.
For USART MSPIM mode of operation only internal clock generation (i.e. master
operation) is supported. The Data Direction Register for the XCKn pin (DDR_XCKn)
must therefore be set to one (i.e. as output) for the USART in MSPIM to operate
correctly. Preferably the DDR_XCKn should be set up before the USART in MSPIM is
enabled (i.e. TXENn and RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART
synchronous master mode. The baud rate or UBRRn setting can therefore be
calculated using the same equations, see
Table 24-1. Equations for Calculating Baud Rate Register Setting
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial
data, which are determined by control bits UCPHAn and UCPOLn. The data transfer
timing diagrams are shown in
in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to
stabilize. The UCPOLn and UCPHAn functionality is summarized in
Note that changing the setting of any of these bits will corrupt all ongoing
communication for both the receiver and transmitter.
Figure 24-1. UCPHAn and UCPOLn data transfer timing diagrams
Table 24-2. UCPOLn and UCPHAn Functionality
Synchronous Master mode
UCPOLn
0
0
1
Operating Mode
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
The Baud rate is defined to be the transfer rate in bit per second (bps)
BAUD
f
UBRRn Contents of the UBRRHn and UBRRLn Registers, (0-4095)
OSC
UCPHAn
0
1
0
Baud rate (in bits per second, bps)
System Oscillator clock frequency
UCPOL=0
SPI Mode
0
1
2
Figure 24-1
Equation for Calculating
Baud Rate
BAUD
=
(1)
( 2
Table 24-1
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
below. Data bits are shifted out and latched
UBRRn
f
OSC
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
+
below:
) 1
Equation for Calculating
UBRR Value
UBRRn
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
8266B-MCU Wireless-03/11
UCPOL=1
Table 24-2
=
2
BAUD
f
OSC
below.
−
1