ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 381

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.3.5 Combining Address and Data Packets into a Transmission
Figure 25-6. Typical Data Transmission
SDA
25.4 Multi-master Bus Systems, Arbitration and Synchronization
SCL
8266B-MCU Wireless-03/11
START
Addr MSB
1
2
SLA+R/W
pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line
high, a NACK is signaled. When the Receiver has received the last byte, or for some
reason cannot receive any more bytes, it should inform the Transmitter by sending a
NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 25-5. Data Packet Format
Aggregate
Transmitter
A transmission basically consists of a START condition, a SLA+R/W, one or more data
packets and a STOP condition. An empty message, consisting of a START followed by
a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to
implement handshaking between the Master and the Slave. The Slave can extend the
SCL low period by pulling the SCL line low. This is useful if the clock speed set up by
the Master is too fast for the Slave, or the Slave needs extra time for processing
between the data transmissions. The Slave extending the SCL low period will not affect
the SCL high period, which is determined by the Master. As a consequence, the Slave
can reduce the TWI data transfer speed by prolonging the SCL duty cycle.
Figure 25-6 below
be transmitted between the SLA+R/W and the STOP condition, depending on the
software protocol implemented by the application software.
The TWI protocol allows bus systems with several masters. Special concerns have
been taken in order to ensure that transmissions will proceed as normal, even if two or
more masters initiate a transmission at the same time. Two problems arise in multi-
master systems:
SDA from
SDA from
SCL from
Receiver
Master
Addr LSB
SDA
SLA+R/W
7
R/W
8
ACK
9
shows a typical data transmission. Note that several data bytes can
Data MSB
1
2
Data MSB
1
Data Byte
2
7
Data Byte
Data LSB
ATmega128RFA1
8
7
ACK
9
Data LSB
8
ACK
9
STOP, REPEATED
START or Next
Data Byte
STOP
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