ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 121

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.24 XAH_CTRL_1 – Transceiver Acknowledgment Frame Control Register 1
8266B-MCU Wireless-03/11
This register is a multi-purpose control register for various RX_AACK settings.
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 5 – AACK_FLTR_RES_FT - Filter Reserved Frames
This
AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as
specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4
section 7.2.1.1.1. If AACK_FLTR_RES_FT = 0 a received, reserved frame is only
checked for a valid FCS.
• Bit 4 – AACK_UPLD_RES_FT - Process Reserved Frames
If AACK_UPLD_RES_FT = 1 received frames indicated as reserved are further
processed. A RX_END interrupt is generated if the FCS of those frames is valid. In
conjunction with the configuration bit AACK_FLTR_RES_FT set, these frames are
handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction. An
AMI interrupt is issued if the address in the received frame matches the node address.
That means if a reserved frame passes the third level filter rules, an acknowledgment
frame is generated and transmitted if it was requested by the received frame. If this is
not wanted bit AACK_DIS_ACK in register CSMA_SEED_1 has to be set.
• Bit 3 – Res - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 2 – AACK_ACK_TIME - Reduce Acknowledgment Time
According to IEEE 802.15.4, section 7.5.6.4.2 the transmission of an acknowledgment
frame shall commence 12 symbols (aTurnaroundTime) after the reception of the last
symbol of a data or MAC command frame. This is achieved with the reset value of the
register bit AACK_ACK_TIME. If AACK_ACK_TIME = 1 an acknowledgment frame is
alternatively sent already 2 symbol periods (32 µs) after the reception of the last symbol
of a data or MAC command frame. This may be applied to proprietary networks or
networks using the High Data Rate Modes to increase battery lifetime and to improve
the overall data throughput. This setting affects also to acknowledgment frame
response time for slotted acknowledgment operation.
Bit
NA ($157)
Read/Write
Initial Value
Bit
NA ($157)
Read/Write
Initial Value
Register Bits
register
Res1
R
Res
7
0
R
bit
3
0
shall
AACK_ACK_TIME AACK_PROM_MODE
Res0
R
6
0
only
RW
2
0
Value
0xF
AACK_FLTR_RES_FT AACK_UPLD_RES_FT
be
set
RW
5
0
Description
RSSI > -51 dBm
RX_THRES > RSSI_BASE_VAL + 14 · 3;
RSSI > -48 dBm
RW
if
1
0
AACK_UPLD_RES_FT
ATmega128RFA1
RW
4
0
Res
R
0
0
XAH_CTRL_1
XAH_CTRL_1
=
1.
121
If