ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 115

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.18 IRQ_MASK – Transceiver Interrupt Enable Register
8266B-MCU Wireless-03/11
according to bits ANT_CTRL if the Antenna Diversity algorithm is disabled. Do not
enable Antenna Diversity RF switch control (ANT_EXT_SW_EN = 1) and RX Frame
Time Stamping (IRQ_2_EXT_EN = 1, see register TRX_CTRL_1) at the same time. If
this bit is set the control pins DIG1/DIG2 are activated in all radio transceiver states as
long as bit ANT_EXT_SW_EN is also set. If the radio transceiver is not in a receive or
transmit state, it is recommended to disable bit ANT_EXT_SW_EN to reduce the power
consumption or avoid leakage current of an external RF switch especially during
SLEEP state. The output pins DIG1 and DIG2 are pulled-down to digital ground if bit
ANT_EXT_SW_EN = 0.
Table 9-49 ANT_EXT_SW_EN Register Bits
• Bit 1:0 – ANT_CTRL1:0 - Static Antenna Diversity Switch Control
These bits provide a static control of an Antenna Diversity switch. This register setting
defines the selected antenna if ANT_DIV_EN is set to 0 (Antenna Diversity disabled).
Register values 1 and 2 are valid for ANT_EXT_SW_EN = 1.
Table 9-50 ANT_CTRL Register Bits
This register is used to enable or disable individual interrupts of the radio transceiver.
An interrupt is enabled if the corresponding bit is set to 1. All interrupts are disabled
after the power up sequence or reset. If an interrupt is enabled it is recommended to
read the interrupt status register IRQ_STATUS first to clear the history.
• Bit 7 – AWAKE_EN - Awake Interrupt Enable
• Bit 6 – TX_END_EN - TX_END Interrupt Enable
• Bit 5 – AMI_EN - Address Match Interrupt Enable
• Bit 4 – CCA_ED_DONE_EN - End of ED Measurement Interrupt Enable
• Bit 3 – RX_END_EN - RX_END Interrupt Enable
Bit
NA ($14E)
Read/Write
Initial Value
Bit
NA ($14E)
Read/Write
Initial Value
Register Bits
ANT_EXT_SW_EN
Register Bits
ANT_CTRL1:0
RX_END_EN
AWAKE_EN
RW
RW
7
0
3
0
RX_START_EN
TX_END_EN
RW
RW
6
0
2
0
Value
Value
0
1
0
1
2
3
PLL_UNLOCK_EN
AMI_EN
RW
Description
Antenna Diversity RF switch control disabled
Antenna Diversity RF switch control enabled
Description
Reserved
Antenna 1: DIG1=H, DIG2=L
Antenna 0: DIG1=L, DIG2=H
Default value for ANT_EXT_SW_EN=0;
Mandatory setting for applications not using
Antenna Diversity
5
0
RW
1
0
ATmega128RFA1
CCA_ED_DONE_EN
PLL_LOCK_EN
RW
4
0
RW
0
0
IRQ_MASK
IRQ_MASK
115