ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 84

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.6.6.4 Interrupt Handling
9.6.6.5 RF Channel Selection
9.6.7 Automatic Filter Tuning (FTN)
9.7 Radio Transceiver Usage
84
ATmega128RFA1
changes significantly. Both calibration loops can be initiated manually by setting
PLL_CF_START = 1 of register PLL_CF and PLL_DCU_START = 1 of register
PLL_DCU. The device must be in PLL_ON or RX_ON state to start the calibration. The
completion of the center frequency tuning is indicated by a TRX24_PLL_LOCK
interrupt.
Both calibration loops may be run simultaneously.
Two different interrupts indicate the PLL status. The TRX24_PLL_LOCK interrupt
indicates that the PLL has locked. The TRX24_PLL_UNLOCK interrupt indicates an
unexpected unlock condition.
A TRX24_PLL_LOCK interrupt is supposed to occur in the following situations:
• State change from TRX_OFF to PLL_ON / RX_ON/ RX_AACK_ON/
• Channel change in states PLL_ON / RX_ON/ RX_AACK_ON/ TX_ARET_ON;
Any other occurrences of PLL interrupts indicate erroneous behavior and require
checking of the actual device status.
The state transition from BUSY_TX to PLL_ON after successful transmission does not
generate a TRX24_PLL_LOCK interrupt within the settling period.
The PLL is designed to support 16 channels in the 2.4 GHz ISM band with channel
spacing of 5 MHz according to IEEE 802.15.4. The center frequency of these channels
is defined as follows:
F
where k is the channel number.
The channel k is selected by the CHANNEL bits of register PHY_CC_CA.
The FTN is incorporated to compensate device tolerances for temperature, supply
voltage variations as well as part-to-part variations of the radio transceiver. The filter-
tuning result is used to correct the transfer function of the analog baseband filter and
the time constant of the PLL loop-filter (refer to
31).
An FTN calibration cycle is initiated automatically when entering the radio transceiver
TRX_OFF state from the SLEEP or RESET state.
Although receiver and transmitter are very robust against these variations, it is
recommended to initiate the FTN manually if the radio transceiver does not use the
SLEEP state. A calibration cycle is to be initiated in states TRX_OFF, PLL_ON or
RX_ON if necessary. This applies in particular to the High Data Rate Modes with a
much higher sensitivity to variations of the BPF transfer function. The recommended
calibration interval is 5 min or less.
This section describes the basic procedures to receive and transmit frames with the
radio transceiver.
c
= 2405 + 5 (k – 11) in [MHz], for k = 11, 12 ... 26
TX_ARET_ON;
"General Circuit Description" on page
8266B-MCU Wireless-03/11