ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 38

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4.1.2.6 RESET State
9.4.1.3 Interrupt Handling
38
ATmega128RFA1
During the transition to BUSY_TX state, the PLL frequency shifts to the transmit
frequency. The actual transmission of the first data chip of the SHR starts after 16 µs to
allow PLL settling and PA ramp-up, see
the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame
length of zero, the transmission is aborted.
After the frame transmission has completed, the radio transceiver automatically turns
off the power amplifier, generates a TRX24_TX_END interrupt and returns into PLL_ON
state.
The RESET state is used to set back the state machine and to reset all registers of the
radio transceiver to their default values.
A reset forces the radio transceiver into the TRX_OFF state.
A reset is initiated by a ATmega128RFA1 main reset (see
176) or a radio transceiver reset (see
During radio transceiver reset the TRXPR register is not cleared and therefore the
application software has to set the SLPTR bit to “0”.
All interrupts provided by the radio transceiver are supported in Basic Operating Mode
(see
Required interrupts must be enabled by writing to register IRQ_MASK and the global
interrupt enable flag must be set. For a general explanation of the interrupt handling
refer to
For example, interrupts are provided to observe the status of the RX and TX operations.
On receive the TRX24_RX_START interrupt indicates the detection of a valid PHR, the
TRX24_XAH_AMI interrupt an address match and the TRX24_RX_END interrupt the
completion of the frame reception.
On transmit the TRX24_TX_END interrupt indicates the completion of the frame
transmission.
Figure 9-13 on
two devices and the related interrupt events in Basic Operating Mode. Device 1
transmits a frame containing a MAC header (in this example of length 7), payload and
valid FCS. The frame is received by Device 2 which generates the interrupts during the
processing of the incoming frame. The received frame is stored in the Frame Buffer.
If the received frame passes the address filter (refer to section
page
the MAC header (MHR).
In Basic Operating Mode the TRX24_RX_END interrupt is issued at the end of the
received frame. In Extended Operating Mode (refer to
page
the FCS is valid. Further exceptions are explained in
page
Processing delay t
Characteristics" on page
Table 9-2 on page
43.
43) the interrupt is only issued if the received frame passes the address filter and
54) an address match TRX24_XAH_AMI interrupt is issued after the reception of
"Reset and Interrupt Handling" on page 15
page 39 shows an example for a transmit/receive transaction between
IRQ
34).
is a typical value (see chapter
507).
"Transceiver Pin Register TRXPR" on page
Figure 9-16 on page
and
"Interrupt Logic" on page
"Extended Operating Mode" on
"Extended Operating Mode" on
"Resetting the AVR" on page
"Digital Interface Timing
40. After transmission of
"Frame Filtering" on
8266A-MCU Wireless-12/09
33.
32).