ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 357
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 357 of 524
- Download datasheet (5Mb)
23.10.3 UCSR0B – USART0 Control and Status Register B
8266A-MCU Wireless-12/09
• Bit 5 – UDRE0 - USART Data Register Empty
The UDRE0 Flag indicates if the transmit buffer (UDR0) is ready to receive new data. If
UDRE0 is one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag
can generate a Data Register Empty interrupt (see description of the UDRIE0 bit).
UDRE0 is set after a reset to indicate that the Transmitter is ready.
• Bit 4 – FE0 - Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when
received. I.e., when the first stop bit of the next character in the receive buffer is zero.
This bit is valid until the receive buffer (UDR0) is read. The FE0 bit is zero when the
stop bit of received data is one. Always set this bit to zero when writing to UCSR0A.
• Bit 3 – DOR0 - Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when
the receive buffer is full (two characters), it is a new character waiting in the Receive
Shift Register and a new start bit is detected. This bit is valid until the receive buffer
(UDR0) is read. Always set this bit to zero when writing to UCSR0A.
• Bit 2 – UPE0 - USART Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received
and the Parity Checking was enabled at that point (UPM01 = 1). This bit is valid until the
receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.
• Bit 1 – U2X0 - Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using
synchronous operation. Writing this bit to one will reduce the divisor of the baud rate
divider from 16 to 8 effectively doubling the transfer rate for asynchronous
communication.
• Bit 0 – MPCM0 - Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM0 bit is
written to one, all the incoming frames received by the USART Receiver that do not
contain address information will be ignored. The Transmitter is unaffected by the
MPCM0 setting. For more detailed information see section "Multi-processor
Communication Mode".
• Bit 7 – RXCIE0 - RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC0 Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXC0 bit in UCSR0A is set.
• Bit 6 – TXCIE0 - TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC0 Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXC0 bit in UCSR0A is set.
• Bit 5 – UDRIE0 - USART Data Register Empty Interrupt Enable
Bit
NA ($C1)
Read/Write
Initial Value
RXCIE0
RW
7
0
TXCIE0
RW
6
0
UDRIE0
RW
5
1
RXEN0
RW
4
0
TXEN0
RW
3
0
ATmega128RFA1
UCSZ02
RW
2
0
RXB80
R
1
0
TXB80
W
0
0
UCSR0B
357
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