ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 160

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.4.5 Watchdog Timer
12.4.6 Port Pins
12.4.7 On-chip Debug System
12.4.8 Symbol Counter
12.4.9 Radio Transceiver
160
ATmega128RFA1
used immediately. Refer to
start-up time.
If the Watchdog Timer is not needed in the application, the module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,
always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to
how to configure the Watchdog Timer.
When entering a sleep mode, all port pins should be configured to use minimum power.
The most important is then to ensure that no pins drive resistive loads. In sleep modes
where both the I/O clock (clk
buffers of the device will be disabled. This ensures that no power is consumed by the
input logic when not needed. In some cases, the input logic is needed for detecting
wake-up conditions, and it will then be enabled. Refer to the section
186
signal is left floating or have an analog signal level close to DEVDD/2, the input buffer
will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog
signal level close to DEVDD/2 on an input pin can cause significant current even in
active mode. Digital input buffers can be disabled by writing to the Digital Input Disable
Registers DIDR1 and DIDR0. Refer to
page 409
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep
mode, the main clock source is enabled, and hence, always consumes power. In the
deeper sleep modes, this will contribute significantly to the total current consumption.
There are three alternative ways to disable the OCD system:
• Disable the OCDEN Fuse.
• Disable the JTAGEN Fuse.
• Write one to the JTD bit in MCUCR.
The Symbol Counter acts as a separate counter, which uses either the 16MHz clock
from XTAL1/XTAL2 crystal pins or the clock from PG3/PG4 low frequency crystal pins.
If the Symbol Counter module is not used, it should be disabled, see section
Symbol Counter" on page
The radio transceiver module is automatically starting its state machine after power on.
While the CPU is in any sleep mode, the radio transceiver remains active. This enables
the radio transceiver to wakeup the MCU if a pending action is over (frame received or
transmission completed). The radio transceiver will be inactive during sleep, if either the
its power reduction bit PRTRX24 in register PRR1 is set or it is send into SLEEP mode,
see
The radio transceiver is derived from a stand alone solution that was partly controlled
by external pins. Now the radio transceiver is fully controlled by individual register bits.
"PRR1 – Power Reduction Register 1" on page 168
for details on which pins are enabled. If the input buffer is enabled and the input
and
"DIDR0 – Digital Input Disable Register 0" on page 433
133.
"Internal Voltage Reference" on page 179
I/O
) and the ADC clock (clk
"DIDR1 – Digital Input Disable Register 1" on
"Watchdog Timer" on page 180
for details.
ADC
) are stopped, the input
8266A-MCU Wireless-12/09
"I/O-Ports" on page
for details.
for details on the
for details on
"MAC