ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 163

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.5.2 SRAM with Data Retention
12.5.3 Voltage Regulators (AVREG, DVREG)
8266A-MCU Wireless-12/09
It is necessary to prevent any data loss of the SRAM when setting the CPU in one of
the sleep modes. For that purpose the SRAM blocks will not be completely switched off
if the power-chain is disabled. Instead the supply voltage for any individual SRAM block
is decreased to reduce its leakage current but guaranteeing its data retention.
The SRAM memory is divided into four separate blocks. Each block can be fully
switched off by setting the correspondent bit (PRRAM0 ... PRRAM3) in register PRR2
(see
software to switch off unused SRAM memory to save power and to reduce leakage
currents.
Every SRAM block can be enabled again by resetting the respective bit (PRRAM0 ...
PRRAM3) of register PRR2. For each SRAM block n the bit DRTSWOK of the
corresponding register DRTRAMn shows the state of the DRT switch (logic high means
SRAM block can be accessed).
If the power-chain is switched off during deep-sleep modes, the content of the SRAM
blocks must be sustained. To provide data retention and lowest leakage current, a data
retention block controls the SRAM behavior during deep-sleep. Since the leakage
current is dramatically depending from the voltage of the SRAM, the supply voltage can
be decreased by enabling the data retention mode DRT.
Every SRAM block n is controlled by its assigned register DRTRAMn. The bit ENDRT
enables the data retention mode during deep-sleep. If this bit is zero, the respective
SRAM block is completely switched off.
Table 12-3. SRAM behavior while in deep-sleep mode
The lower 4-bit of the register DRTRAMn are reserved and should not be changed. The
reset value of the DRT voltage settings are preprogrammed during the manufacturing
process and need not to be changed.
The main features of the Voltage Regulator blocks are:
• Bandgap stabilized 1.8V supply for analog and digital domain;
AVR State
off
DEEP SLEEP
Notes:
ENDRT
1
0
1
0
(2,3)
"PRR2 – Power Reduction Register 2" on page
Power-chain
ON
ON
off
off
1. Idle
2. Power Down
3. Power Save
4. ADC Noise Reduction Mode
5. Standby
6. Extended Standby
7.
Radio Transceiver State
off (SLEEP or power reduction)
SRAM supply voltage
1.8V (DVDD)
1.8V (DVDD)
Reduced
Disconnected
ATmega128RFA1
168). This enables the application
Powerchain
off
(7)
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