ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 154

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.11.2 CLKPR – Clock Prescale Register
154
ATmega128RFA1
• Bit 7 – CLKPCE - Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits
are written. Rewriting the CLKPCE bit within this time-out period does neither extend
the time-out period, nor clear the CLKPCE bit.
• Bit 6:4 – Res2:0 - Reserved
• Bit 3:0 – CLKPS3:0 - Clock Prescaler Select Bits
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The
division factors are given in the following table. Note that the factor is different when
using the internal 16MHz RC oscillator as the clock source. The CKDIV8 Fuse
determines the initial value of the CLKPS bits. If CKDIV8 is not programmed, the
CLKPS bits will be reset to 0000. If CKDIV8 is programmed, CLKPS bits are reset to
0011 giving a division factor of 8 at start up. This feature should be used if the selected
clock source has a higher frequency than the maximum frequency of the device at the
present operating conditions. Note that any value can be written to the CLKPS bits
regardless of the CKDIV8 Fuse setting. The Application software must ensure that a
sufficient division factor is chosen if the selected clock source has a higher frequency
than the maximum frequency of the device at the present operating conditions. The
device is shipped with the CKDIV8 Fuse programmed.
Table 11-12 CLKPS Register Bits
Bit
NA ($61)
Read/Write
Initial Value
Register Bits
Register Bits
CLKPS3:0
CLKPCE
RW
7
0
Res2
R
6
0
Res1
R
5
0
Value
Value
0xA
0xff
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
Res0
R
4
0
CLKPS3 CLKPS2 CLKPS1 CLKPS0
Description
Calibration value for highest oscillator
frequency
Description
Division factor 1 / RC-Oscillator 2
Division factor 2 / RC-Oscillator 4
Division factor 4 / RC-Oscillator 8
Division factor 8 / RC-Oscillator 16
Division factor 16 / RC-Oscillator 32
Division factor 32 / RC-Oscillator 64
Division factor 64 / RC-Oscillator 128
Division factor 128 / RC-Oscillator 256
Division factor 256 / RC-Oscillator 512
Reserved
Reserved
RW
3
0
RW
2
0
RW
1
0
8266A-MCU Wireless-12/09
RW
0
0
CLKPR