ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 415

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.5.3 Conversion Timing
8266A-MCU Wireless-12/09
Figure 27-4. ADC Timing Diagram, Start-Up for Single Ended Channels
Figure 27-5. ADC Timing Diagram, Start-Up for Differential Channels
The delay from requesting a conversion start by setting the ADSC bit in ADCSRA to the
moment where the sample-and-hold takes place is fixed. The same fixed delay also
applies for auto triggered conversions. In this case three additional CPU clock cycles
are used for the trigger event synchronization logic. The delay depends on the
prescaler configuration ADPS and if single-ended or differential channels are used. A
summary is given in
When a conversion is complete, the result is written to the ADC Data Registers, and
ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software
may then set ADSC again, and a new conversion will be initiated at the earliest after the
following tracking phase. The tracking phase is required after each conversion. Its
duration can be adjusted according to the ADC clock speed by the ADTHT bits in
ADCSRC and is different for single-ended and differential channels. For details see
Table 27-4 on
In Free Running mode, a new conversion will be started immediately after the tracking
phase of the previous conversion while ADSC remains high. The calculation of the
resulting sample rate is given
For timing diagrams of single and auto triggered and free running conversions see
Figure 27-6 on
A D C C lo c k
A D E N
A V D D O K
A D S C
A D IF
A D C H
A D C L
A D C C lo c k
A D E N
A V D D O K
A D S C
A D IF
A D C H
A D C L
Parameter
Gain Amplifier Initialization Time t
M U X a n d R E F S U p d a te
M U X a n d R E F S U p d a te
P o w e r -U p
P o w e r -U p
A V D D
t
A V D D
t
A V P U
A V P U
page 416.
page 416 to
Table 27-3 on
S ta r t -U p
S t a rt -U p
A D C
t
A D S U
A D C
t
A D S U
Figure 27-8 on
in Table 27-5 on
AINIT
A m p lifie r
t
A IN IT
In it
page 416. All conversions take 11 ADC clock cycles.
S a m p le
& H o ld
page 417.
Duration in ADC Clock Cycles
2(ADTHT+2)
1 1 T
C o n v e rs io n
S a m p le
& H o ld
page 416.
A D C _ C L K
C o n v e rs io n
C o m p le te
ATmega128RFA1
1 1 T
C o n v e r s io n
A D C _ C L K
C o n v e rs io n
C o m p le te
S ig n a n d M S B o f R e s u lt
L S B o f R e s u lt
S ig n a n d M S B
L S B o f R e s u lt
415